diff --git a/design/dec/el2_dec_decode_ctl.sv b/design/dec/el2_dec_decode_ctl.sv
index 1878081..7d71917 100644
--- a/design/dec/el2_dec_decode_ctl.sv
+++ b/design/dec/el2_dec_decode_ctl.sv
@@ -602,7 +602,6 @@ end // else: !if(pt.BTB_ENABLE==1)
 
    always_comb begin
       found = 0;
-      cam_wen[NBLOAD_SIZE_MSB:0] = '0;
       for (int i=0; i<NBLOAD_SIZE; i++) begin
          if (~found) begin
             if (~cam[i].valid) begin
@@ -618,7 +617,6 @@ end // else: !if(pt.BTB_ENABLE==1)
       end
    end
 
-
    assign cam_write          = lsu_nonblock_load_valid_m;
    assign cam_write_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_tag_m[NBLOAD_TAG_MSB:0];
 
diff --git a/tools/Makefile b/tools/Makefile
index aaeeedc..9901a7a 100755
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -34,7 +34,7 @@ IRUN = xrun
 VCS = vcs
 VLOG = qverilog
 VERILATOR = verilator
-RIVEIRA = riviera
+RIVIERA = riviera
 GCC_PREFIX = riscv64-unknown-elf
 BUILD_DIR = snapshots/${snapshot}
 TBDIR = ${RV_ROOT}/testbench
@@ -103,7 +103,7 @@ all: clean verilator
 clean:
 	rm -rf *.log *.s *.hex *.dis *.tbl irun* vcs* simv* snapshots swerv* \
 	verilator* *.exe obj* *.o ucli.key vc_hdrs.h csrc *.csv work\
-	work dataset.asdb  library.cfg vsimsa.cfg  riviera-build wave.asdb
+	dataset.asdb  library.cfg vsimsa.cfg  riviera-build wave.asdb