Delete no use files in toos.
This commit is contained in:
colin
parent
d86fef92e2
commit
9950499ac5
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@ -1,26 +0,0 @@
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@80000000
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73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30
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B7 50 55 5F 93 80 50 55 73 90 00 7C B7 01 58 D0
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17 02 00 00 13 02 E2 0E 83 02 02 00 23 80 51 00
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05 02 E3 9B 02 FE B7 01 58 D0 93 02 F0 0F 23 80
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51 00 E3 0A 00 FE 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
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01 00 01 00 01 00 01 00 01 00 01 00 01 00
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@8000010E
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2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
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2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
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2D 2D 0A 48 65 6C 6C 6F 20 57 6F 72 6C 64 20 66
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72 6F 6D 20 53 77 65 52 56 20 45 4C 32 20 40 57
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44 43 20 21 21 0A 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
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2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
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2D 2D 2D 2D 2D 2D 2D 2D 0A 00
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@ -1,247 +0,0 @@
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
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// This is an automatically generated file by colin on Mon Mar 7 04:09:03 AM UTC 2022
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//
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// cmd: swerv -target=default -set build_axi4
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//
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`define RV_ROOT "/home/colin/develop/Cores-SweRV-EL2"
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`define RV_NMI_VEC 'h11110000
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`define RV_NUMIREGS 32
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`define RV_BHT_GHR_RANGE 7:0
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`define RV_BHT_HASH_STRING {hashin[8+1:2]^ghr[8-1:0]}// cf2
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`define RV_BHT_ADDR_HI 9
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`define RV_BHT_GHR_SIZE 8
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`define RV_BHT_ARRAY_DEPTH 256
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`define RV_BHT_GHR_HASH_1
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`define RV_BHT_SIZE 512
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`define RV_BHT_ADDR_LO 2
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`define RV_RET_STACK_SIZE 8
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`define RV_CONFIG_KEY 32'hdeadbeef
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`define RV_TARGET default
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`define RV_DCCM_OFFSET 28'h40000
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`define RV_DCCM_REGION 4'hf
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`define RV_DCCM_EADR 32'hf004ffff
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`define RV_DCCM_SIZE 64
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`define RV_DCCM_SADR 32'hf0040000
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`define RV_DCCM_FDATA_WIDTH 39
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`define RV_DCCM_BANK_BITS 2
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`define RV_DCCM_NUM_BANKS_4
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`define RV_DCCM_ROWS 4096
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`define RV_DCCM_ENABLE 1
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`define RV_DCCM_INDEX_BITS 12
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`define RV_DCCM_BITS 16
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`define RV_DCCM_NUM_BANKS 4
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`define RV_LSU_SB_BITS 16
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`define RV_DCCM_DATA_WIDTH 32
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`define RV_DCCM_DATA_CELL ram_4096x39
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`define RV_DCCM_RESERVED 'h1400
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`define RV_DCCM_SIZE_64
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`define RV_DCCM_ECC_WIDTH 7
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`define RV_DCCM_WIDTH_BITS 2
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`define RV_DCCM_BYTE_WIDTH 4
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`define REGWIDTH 32
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`define RV_RESET_VEC 'h80000000
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`define RV_LSU_STBUF_DEPTH 4
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`define RV_BITMANIP_ZBR 0
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`define RV_BITMANIP_ZBS 1
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`define RV_BITMANIP_ZBF 0
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`define RV_FPGA_OPTIMIZE 1
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`define RV_DMA_BUF_DEPTH 5
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`define RV_BITMANIP_ZBC 1
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`define RV_BITMANIP_ZBE 0
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`define RV_ICCM_ICACHE 1
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`define RV_FAST_INTERRUPT_REDIRECT 1
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`define RV_LSU_NUM_NBLOAD 4
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`define RV_BITMANIP_ZBA 1
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`define RV_BITMANIP_ZBP 0
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`define RV_LSU2DMA 0
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`define RV_LSU_NUM_NBLOAD_WIDTH 2
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`define RV_DIV_BIT 4
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`define RV_BITMANIP_ZBB 1
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`define RV_TIMER_LEGAL_EN 1
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`define RV_DIV_NEW 1
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`define RV_SERIALIO 'hd0580000
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`define RV_EXTERNAL_DATA 'hc0580000
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`define RV_UNUSED_REGION5 'h30000000
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`define RV_UNUSED_REGION4 'h40000000
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`define RV_UNUSED_REGION1 'h70000000
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`define RV_UNUSED_REGION8 'h00000000
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`define RV_UNUSED_REGION2 'h60000000
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`define RV_UNUSED_REGION7 'h10000000
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`define RV_DEBUG_SB_MEM 'ha0580000
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`define RV_UNUSED_REGION6 'h20000000
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`define RV_UNUSED_REGION3 'h50000000
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`define RV_EXTERNAL_DATA_1 'hb0000000
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`define RV_UNUSED_REGION0 'h90000000
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`define RV_ICCM_NUM_BANKS 4
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`define RV_ICCM_BITS 16
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`define RV_ICCM_INDEX_BITS 12
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`define RV_ICCM_ENABLE 1
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`define RV_ICCM_SIZE_64
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`define RV_ICCM_DATA_CELL ram_4096x39
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`define RV_ICCM_RESERVED 'h1000
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`define RV_ICCM_BANK_INDEX_LO 4
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`define RV_ICCM_SADR 32'hee000000
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`define RV_ICCM_EADR 32'hee00ffff
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`define RV_ICCM_OFFSET 10'he000000
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`define RV_ICCM_REGION 4'he
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`define RV_ICCM_SIZE 64
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`define RV_ICCM_NUM_BANKS_4
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`define RV_ICCM_ROWS 4096
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`define RV_ICCM_BANK_HI 3
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`define RV_ICCM_BANK_BITS 2
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`define RV_PIC_MEIPL_MASK 'hf
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`define RV_PIC_MEIPL_COUNT 31
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`define RV_PIC_MEIE_COUNT 31
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`define RV_PIC_MEIP_MASK 'h0
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`define RV_PIC_MEIPT_OFFSET 'h3004
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`define RV_PIC_REGION 4'hf
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`define RV_PIC_TOTAL_INT 31
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`define RV_PIC_MEIGWCTRL_OFFSET 'h4000
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`define RV_PIC_MEIP_COUNT 1
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`define RV_PIC_MEIE_MASK 'h1
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`define RV_PIC_MPICCFG_OFFSET 'h3000
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`define RV_PIC_MEIGWCLR_MASK 'h0
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`define RV_PIC_MEIGWCLR_COUNT 31
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`define RV_PIC_INT_WORDS 1
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`define RV_PIC_OFFSET 10'hc0000
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`define RV_PIC_MEIP_OFFSET 'h1000
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`define RV_PIC_BITS 15
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`define RV_PIC_MPICCFG_COUNT 1
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`define RV_PIC_MEIGWCLR_OFFSET 'h5000
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`define RV_PIC_SIZE 32
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`define RV_PIC_MPICCFG_MASK 'h1
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`define RV_PIC_TOTAL_INT_PLUS1 32
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`define RV_PIC_MEIPL_OFFSET 'h0000
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`define RV_PIC_MEIGWCTRL_COUNT 31
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`define RV_PIC_BASE_ADDR 32'hf00c0000
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`define RV_PIC_MEIPT_MASK 'h0
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`define RV_PIC_MEIE_OFFSET 'h2000
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`define RV_PIC_MEIGWCTRL_MASK 'h3
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`define RV_PIC_MEIPT_COUNT 31
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`define RV_INST_ACCESS_ADDR2 'h00000000
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`define RV_DATA_ACCESS_MASK6 'hffffffff
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`define RV_DATA_ACCESS_ENABLE0 1'h0
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`define RV_INST_ACCESS_ENABLE4 1'h0
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`define RV_INST_ACCESS_MASK1 'hffffffff
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`define RV_INST_ACCESS_ADDR5 'h00000000
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`define RV_INST_ACCESS_ENABLE1 1'h0
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`define RV_INST_ACCESS_MASK4 'hffffffff
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`define RV_DATA_ACCESS_ADDR2 'h00000000
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`define RV_INST_ACCESS_MASK6 'hffffffff
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`define RV_INST_ACCESS_ENABLE0 1'h0
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`define RV_DATA_ACCESS_ADDR5 'h00000000
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`define RV_DATA_ACCESS_MASK1 'hffffffff
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`define RV_DATA_ACCESS_ENABLE4 1'h0
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`define RV_DATA_ACCESS_ENABLE1 1'h0
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`define RV_DATA_ACCESS_MASK4 'hffffffff
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`define RV_DATA_ACCESS_ENABLE6 1'h0
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`define RV_INST_ACCESS_MASK7 'hffffffff
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`define RV_INST_ACCESS_ENABLE5 1'h0
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`define RV_DATA_ACCESS_MASK0 'hffffffff
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`define RV_INST_ACCESS_ADDR3 'h00000000
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`define RV_INST_ACCESS_ENABLE6 1'h0
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`define RV_DATA_ACCESS_MASK7 'hffffffff
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`define RV_DATA_ACCESS_ENABLE5 1'h0
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`define RV_INST_ACCESS_MASK0 'hffffffff
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`define RV_DATA_ACCESS_ADDR3 'h00000000
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`define RV_DATA_ACCESS_ENABLE3 1'h0
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`define RV_DATA_ACCESS_ADDR0 'h00000000
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`define RV_INST_ACCESS_MASK3 'hffffffff
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`define RV_DATA_ACCESS_ENABLE2 1'h0
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`define RV_INST_ACCESS_ADDR7 'h00000000
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`define RV_INST_ACCESS_ENABLE3 1'h0
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`define RV_INST_ACCESS_ADDR0 'h00000000
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`define RV_DATA_ACCESS_MASK3 'hffffffff
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`define RV_DATA_ACCESS_ADDR7 'h00000000
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`define RV_INST_ACCESS_ENABLE2 1'h0
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`define RV_INST_ACCESS_MASK5 'hffffffff
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`define RV_INST_ACCESS_ADDR1 'h00000000
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`define RV_INST_ACCESS_ADDR4 'h00000000
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`define RV_INST_ACCESS_MASK2 'hffffffff
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`define RV_INST_ACCESS_ENABLE7 1'h0
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`define RV_DATA_ACCESS_ADDR6 'h00000000
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`define RV_DATA_ACCESS_ADDR1 'h00000000
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`define RV_DATA_ACCESS_MASK5 'hffffffff
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`define RV_DATA_ACCESS_ADDR4 'h00000000
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`define RV_DATA_ACCESS_MASK2 'hffffffff
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`define RV_DATA_ACCESS_ENABLE7 1'h0
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`define RV_INST_ACCESS_ADDR6 'h00000000
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`define RV_IFU_BUS_PRTY 2
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`define RV_SB_BUS_PRTY 2
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`define RV_LSU_BUS_ID 1
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`define RV_LSU_BUS_TAG 3
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`define RV_SB_BUS_TAG 1
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`define RV_DMA_BUS_ID 1
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`define RV_DMA_BUS_TAG 1
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`define RV_LSU_BUS_PRTY 2
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`define RV_BUS_PRTY_DEFAULT 2'h3
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`define RV_SB_BUS_ID 1
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`define RV_DMA_BUS_PRTY 2
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`define RV_IFU_BUS_ID 1
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`define RV_IFU_BUS_TAG 3
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`define RV_XLEN 32
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`define RV_BTB_INDEX3_LO 18
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`define RV_BTB_INDEX1_LO 2
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`define RV_BTB_ADDR_HI 9
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`define RV_BTB_INDEX2_LO 10
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`define RV_BTB_SIZE 512
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`define RV_BTB_BTAG_FOLD 0
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`define RV_BTB_ADDR_LO 2
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`define RV_BTB_INDEX2_HI 17
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`define RV_BTB_ENABLE 1
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`define RV_BTB_TOFFSET_SIZE 12
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`define RV_BTB_INDEX3_HI 25
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`define RV_BTB_ARRAY_DEPTH 256
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`define RV_BTB_BTAG_SIZE 5
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`define RV_BTB_INDEX1_HI 9
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`define RV_BTB_FOLD2_INDEX_HASH 0
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`define TEC_RV_ICG clockhdr
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`define RV_ASSERT_ON
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`define RV_STERR_ROLLBACK 0
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`define RV_BUILD_AXI4 1
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`define SDVT_AHB 0
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`define RV_EXT_DATAWIDTH 64
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`define RV_EXT_ADDRWIDTH 32
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`define TOP tb_top
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`define RV_LDERR_ROLLBACK 1
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`define RV_BUILD_AXI_NATIVE 1
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`define RV_TOP `TOP.rvtop
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`define CLOCK_PERIOD 100
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`define CPU_TOP `RV_TOP.swerv
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`define RV_ICACHE_INDEX_HI 12
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`define RV_ICACHE_TAG_CELL ram_128x25
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`define RV_ICACHE_NUM_BEATS 8
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`define RV_ICACHE_FDATA_WIDTH 71
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`define RV_ICACHE_NUM_BYPASS_WIDTH 2
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`define RV_ICACHE_TAG_DEPTH 128
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`define RV_ICACHE_TAG_BYPASS_ENABLE 1
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`define RV_ICACHE_SIZE 16
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`define RV_ICACHE_TAG_NUM_BYPASS 2
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`define RV_ICACHE_BANK_WIDTH 8
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`define RV_ICACHE_DATA_INDEX_LO 4
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`define RV_ICACHE_2BANKS 1
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`define RV_ICACHE_NUM_LINES_BANK 64
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`define RV_ICACHE_ECC 1
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`define RV_ICACHE_STATUS_BITS 1
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`define RV_ICACHE_TAG_NUM_BYPASS_WIDTH 2
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`define RV_ICACHE_BEAT_BITS 3
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`define RV_ICACHE_DATA_WIDTH 64
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`define RV_ICACHE_BYPASS_ENABLE 1
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`define RV_ICACHE_WAYPACK 1
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`define RV_ICACHE_NUM_BYPASS 2
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`define RV_ICACHE_DATA_DEPTH 512
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`define RV_ICACHE_BEAT_ADDR_HI 5
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`define RV_ICACHE_TAG_LO 13
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`define RV_ICACHE_BANK_BITS 1
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`define RV_ICACHE_ENABLE 1
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`define RV_ICACHE_BANK_HI 3
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`define RV_ICACHE_NUM_LINES 256
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`define RV_ICACHE_TAG_INDEX_LO 6
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`define RV_ICACHE_LN_SZ 64
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`define RV_ICACHE_NUM_LINES_WAY 128
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`define RV_ICACHE_DATA_CELL ram_512x71
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`define RV_ICACHE_BANKS_WAY 2
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`define RV_ICACHE_NUM_WAYS 2
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`define RV_ICACHE_SCND_LAST 6
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`define RV_ICACHE_BANK_LO 3
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`undef RV_ASSERT_ON
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@ -1,176 +0,0 @@
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// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
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// This is an automatically generated file by colin on Mon Mar 7 04:09:03 AM UTC 2022
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//
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// cmd: swerv -target=default -set build_axi4
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//
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#ifndef RV_NMI_VEC
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#define RV_NMI_VEC 0x11110000
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#endif
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#define RV_TARGET default
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#define RV_DCCM_OFFSET 0x40000
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#define RV_DCCM_REGION 0xf
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#define RV_DCCM_EADR 0xf004ffff
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#define RV_DCCM_SIZE 64
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#define RV_DCCM_SADR 0xf0040000
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#define RV_DCCM_FDATA_WIDTH 39
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#define RV_DCCM_BANK_BITS 2
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#define RV_DCCM_NUM_BANKS_4
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#define RV_DCCM_ROWS 4096
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#define RV_DCCM_ENABLE 1
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#define RV_DCCM_INDEX_BITS 12
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#define RV_DCCM_BITS 16
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#define RV_DCCM_NUM_BANKS 4
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#define RV_LSU_SB_BITS 16
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#define RV_DCCM_DATA_WIDTH 32
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#define RV_DCCM_DATA_CELL ram_4096x39
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#define RV_DCCM_RESERVED 0x1400
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#define RV_DCCM_SIZE_64
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#define RV_DCCM_ECC_WIDTH 7
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#define RV_DCCM_WIDTH_BITS 2
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#define RV_DCCM_BYTE_WIDTH 4
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#ifndef RV_RESET_VEC
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#define RV_RESET_VEC 0x80000000
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#endif
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#define RV_LSU_STBUF_DEPTH 4
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#define RV_BITMANIP_ZBR 0
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#define RV_BITMANIP_ZBS 1
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#define RV_BITMANIP_ZBF 0
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#define RV_FPGA_OPTIMIZE 1
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#define RV_DMA_BUF_DEPTH 5
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#define RV_BITMANIP_ZBC 1
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#define RV_BITMANIP_ZBE 0
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#define RV_ICCM_ICACHE 1
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#define RV_FAST_INTERRUPT_REDIRECT 1
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#define RV_LSU_NUM_NBLOAD 4
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#define RV_BITMANIP_ZBA 1
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#define RV_BITMANIP_ZBP 0
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#define RV_LSU2DMA 0
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#define RV_LSU_NUM_NBLOAD_WIDTH 2
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#define RV_DIV_BIT 4
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#define RV_BITMANIP_ZBB 1
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#define RV_TIMER_LEGAL_EN 1
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#define RV_DIV_NEW 1
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#ifndef RV_SERIALIO
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#define RV_SERIALIO 0xd0580000
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#endif
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||||
#ifndef RV_EXTERNAL_DATA
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#define RV_EXTERNAL_DATA 0xc0580000
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#endif
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#define RV_UNUSED_REGION5 0x30000000
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#define RV_UNUSED_REGION4 0x40000000
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#define RV_UNUSED_REGION1 0x70000000
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#define RV_UNUSED_REGION8 0x00000000
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#define RV_UNUSED_REGION2 0x60000000
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#define RV_UNUSED_REGION7 0x10000000
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#define RV_DEBUG_SB_MEM 0xa0580000
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#define RV_UNUSED_REGION6 0x20000000
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#define RV_UNUSED_REGION3 0x50000000
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#define RV_EXTERNAL_DATA_1 0xb0000000
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#define RV_UNUSED_REGION0 0x90000000
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#define RV_ICCM_NUM_BANKS 4
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#define RV_ICCM_BITS 16
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#define RV_ICCM_INDEX_BITS 12
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#define RV_ICCM_ENABLE 1
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#define RV_ICCM_SIZE_64
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#define RV_ICCM_DATA_CELL ram_4096x39
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#define RV_ICCM_RESERVED 0x1000
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#define RV_ICCM_BANK_INDEX_LO 4
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#define RV_ICCM_SADR 0xee000000
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#define RV_ICCM_EADR 0xee00ffff
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#define RV_ICCM_OFFSET 0xe000000
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#define RV_ICCM_REGION 0xe
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#define RV_ICCM_SIZE 64
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#define RV_ICCM_NUM_BANKS_4
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#define RV_ICCM_ROWS 4096
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#define RV_ICCM_BANK_HI 3
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#define RV_ICCM_BANK_BITS 2
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#define RV_PIC_MEIPL_MASK 0xf
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#define RV_PIC_MEIPL_COUNT 31
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#define RV_PIC_MEIE_COUNT 31
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#define RV_PIC_MEIP_MASK 0x0
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#define RV_PIC_MEIPT_OFFSET 0x3004
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||||
#define RV_PIC_REGION 0xf
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#define RV_PIC_TOTAL_INT 31
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#define RV_PIC_MEIGWCTRL_OFFSET 0x4000
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#define RV_PIC_MEIP_COUNT 1
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#define RV_PIC_MEIE_MASK 0x1
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||||
#define RV_PIC_MPICCFG_OFFSET 0x3000
|
||||
#define RV_PIC_MEIGWCLR_MASK 0x0
|
||||
#define RV_PIC_MEIGWCLR_COUNT 31
|
||||
#define RV_PIC_INT_WORDS 1
|
||||
#define RV_PIC_OFFSET 0xc0000
|
||||
#define RV_PIC_MEIP_OFFSET 0x1000
|
||||
#define RV_PIC_BITS 15
|
||||
#define RV_PIC_MPICCFG_COUNT 1
|
||||
#define RV_PIC_MEIGWCLR_OFFSET 0x5000
|
||||
#define RV_PIC_SIZE 32
|
||||
#define RV_PIC_MPICCFG_MASK 0x1
|
||||
#define RV_PIC_TOTAL_INT_PLUS1 32
|
||||
#define RV_PIC_MEIPL_OFFSET 0x0000
|
||||
#define RV_PIC_MEIGWCTRL_COUNT 31
|
||||
#define RV_PIC_BASE_ADDR 0xf00c0000
|
||||
#define RV_PIC_MEIPT_MASK 0x0
|
||||
#define RV_PIC_MEIE_OFFSET 0x2000
|
||||
#define RV_PIC_MEIGWCTRL_MASK 0x3
|
||||
#define RV_PIC_MEIPT_COUNT 31
|
||||
#define RV_INST_ACCESS_ADDR2 0x00000000
|
||||
#define RV_DATA_ACCESS_MASK6 0xffffffff
|
||||
#define RV_DATA_ACCESS_ENABLE0 0x0
|
||||
#define RV_INST_ACCESS_ENABLE4 0x0
|
||||
#define RV_INST_ACCESS_MASK1 0xffffffff
|
||||
#define RV_INST_ACCESS_ADDR5 0x00000000
|
||||
#define RV_INST_ACCESS_ENABLE1 0x0
|
||||
#define RV_INST_ACCESS_MASK4 0xffffffff
|
||||
#define RV_DATA_ACCESS_ADDR2 0x00000000
|
||||
#define RV_INST_ACCESS_MASK6 0xffffffff
|
||||
#define RV_INST_ACCESS_ENABLE0 0x0
|
||||
#define RV_DATA_ACCESS_ADDR5 0x00000000
|
||||
#define RV_DATA_ACCESS_MASK1 0xffffffff
|
||||
#define RV_DATA_ACCESS_ENABLE4 0x0
|
||||
#define RV_DATA_ACCESS_ENABLE1 0x0
|
||||
#define RV_DATA_ACCESS_MASK4 0xffffffff
|
||||
#define RV_DATA_ACCESS_ENABLE6 0x0
|
||||
#define RV_INST_ACCESS_MASK7 0xffffffff
|
||||
#define RV_INST_ACCESS_ENABLE5 0x0
|
||||
#define RV_DATA_ACCESS_MASK0 0xffffffff
|
||||
#define RV_INST_ACCESS_ADDR3 0x00000000
|
||||
#define RV_INST_ACCESS_ENABLE6 0x0
|
||||
#define RV_DATA_ACCESS_MASK7 0xffffffff
|
||||
#define RV_DATA_ACCESS_ENABLE5 0x0
|
||||
#define RV_INST_ACCESS_MASK0 0xffffffff
|
||||
#define RV_DATA_ACCESS_ADDR3 0x00000000
|
||||
#define RV_DATA_ACCESS_ENABLE3 0x0
|
||||
#define RV_DATA_ACCESS_ADDR0 0x00000000
|
||||
#define RV_INST_ACCESS_MASK3 0xffffffff
|
||||
#define RV_DATA_ACCESS_ENABLE2 0x0
|
||||
#define RV_INST_ACCESS_ADDR7 0x00000000
|
||||
#define RV_INST_ACCESS_ENABLE3 0x0
|
||||
#define RV_INST_ACCESS_ADDR0 0x00000000
|
||||
#define RV_DATA_ACCESS_MASK3 0xffffffff
|
||||
#define RV_DATA_ACCESS_ADDR7 0x00000000
|
||||
#define RV_INST_ACCESS_ENABLE2 0x0
|
||||
#define RV_INST_ACCESS_MASK5 0xffffffff
|
||||
#define RV_INST_ACCESS_ADDR1 0x00000000
|
||||
#define RV_INST_ACCESS_ADDR4 0x00000000
|
||||
#define RV_INST_ACCESS_MASK2 0xffffffff
|
||||
#define RV_INST_ACCESS_ENABLE7 0x0
|
||||
#define RV_DATA_ACCESS_ADDR6 0x00000000
|
||||
#define RV_DATA_ACCESS_ADDR1 0x00000000
|
||||
#define RV_DATA_ACCESS_MASK5 0xffffffff
|
||||
#define RV_DATA_ACCESS_ADDR4 0x00000000
|
||||
#define RV_DATA_ACCESS_MASK2 0xffffffff
|
||||
#define RV_DATA_ACCESS_ENABLE7 0x0
|
||||
#define RV_INST_ACCESS_ADDR6 0x00000000
|
||||
#define RV_XLEN 32
|
||||
#define RV_ASSERT_ON
|
||||
#define RV_STERR_ROLLBACK 0
|
||||
#define RV_BUILD_AXI4 1
|
||||
#define SDVT_AHB 0
|
||||
#define RV_EXT_DATAWIDTH 64
|
||||
#define RV_EXT_ADDRWIDTH 32
|
||||
#define TOP tb_top
|
||||
#define RV_LDERR_ROLLBACK 1
|
||||
#define RV_BUILD_AXI_NATIVE 1
|
||||
#define RV_TOP `TOP.rvtop
|
||||
#define CLOCK_PERIOD 100
|
||||
#define CPU_TOP `RV_TOP.swerv
|
||||
|
|
@ -1,175 +0,0 @@
|
|||
parameter el2_param_t pt = '{
|
||||
BHT_ADDR_HI : 8'h09 ,
|
||||
BHT_ADDR_LO : 6'h02 ,
|
||||
BHT_ARRAY_DEPTH : 15'h0100 ,
|
||||
BHT_GHR_HASH_1 : 5'h00 ,
|
||||
BHT_GHR_SIZE : 8'h08 ,
|
||||
BHT_SIZE : 16'h0200 ,
|
||||
BITMANIP_ZBA : 5'h01 ,
|
||||
BITMANIP_ZBB : 5'h01 ,
|
||||
BITMANIP_ZBC : 5'h01 ,
|
||||
BITMANIP_ZBE : 5'h00 ,
|
||||
BITMANIP_ZBF : 5'h00 ,
|
||||
BITMANIP_ZBP : 5'h00 ,
|
||||
BITMANIP_ZBR : 5'h00 ,
|
||||
BITMANIP_ZBS : 5'h01 ,
|
||||
BTB_ADDR_HI : 9'h009 ,
|
||||
BTB_ADDR_LO : 6'h02 ,
|
||||
BTB_ARRAY_DEPTH : 13'h0100 ,
|
||||
BTB_BTAG_FOLD : 5'h00 ,
|
||||
BTB_BTAG_SIZE : 9'h005 ,
|
||||
BTB_ENABLE : 5'h01 ,
|
||||
BTB_FOLD2_INDEX_HASH : 5'h00 ,
|
||||
BTB_FULLYA : 5'h00 ,
|
||||
BTB_INDEX1_HI : 9'h009 ,
|
||||
BTB_INDEX1_LO : 9'h002 ,
|
||||
BTB_INDEX2_HI : 9'h011 ,
|
||||
BTB_INDEX2_LO : 9'h00A ,
|
||||
BTB_INDEX3_HI : 9'h019 ,
|
||||
BTB_INDEX3_LO : 9'h012 ,
|
||||
BTB_SIZE : 14'h0200 ,
|
||||
BTB_TOFFSET_SIZE : 9'h00C ,
|
||||
BUILD_AHB_LITE : 4'h0 ,
|
||||
BUILD_AXI4 : 5'h01 ,
|
||||
BUILD_AXI_NATIVE : 5'h01 ,
|
||||
BUS_PRTY_DEFAULT : 6'h03 ,
|
||||
DATA_ACCESS_ADDR0 : 36'h000000000 ,
|
||||
DATA_ACCESS_ADDR1 : 36'h000000000 ,
|
||||
DATA_ACCESS_ADDR2 : 36'h000000000 ,
|
||||
DATA_ACCESS_ADDR3 : 36'h000000000 ,
|
||||
DATA_ACCESS_ADDR4 : 36'h000000000 ,
|
||||
DATA_ACCESS_ADDR5 : 36'h000000000 ,
|
||||
DATA_ACCESS_ADDR6 : 36'h000000000 ,
|
||||
DATA_ACCESS_ADDR7 : 36'h000000000 ,
|
||||
DATA_ACCESS_ENABLE0 : 5'h00 ,
|
||||
DATA_ACCESS_ENABLE1 : 5'h00 ,
|
||||
DATA_ACCESS_ENABLE2 : 5'h00 ,
|
||||
DATA_ACCESS_ENABLE3 : 5'h00 ,
|
||||
DATA_ACCESS_ENABLE4 : 5'h00 ,
|
||||
DATA_ACCESS_ENABLE5 : 5'h00 ,
|
||||
DATA_ACCESS_ENABLE6 : 5'h00 ,
|
||||
DATA_ACCESS_ENABLE7 : 5'h00 ,
|
||||
DATA_ACCESS_MASK0 : 36'h0FFFFFFFF ,
|
||||
DATA_ACCESS_MASK1 : 36'h0FFFFFFFF ,
|
||||
DATA_ACCESS_MASK2 : 36'h0FFFFFFFF ,
|
||||
DATA_ACCESS_MASK3 : 36'h0FFFFFFFF ,
|
||||
DATA_ACCESS_MASK4 : 36'h0FFFFFFFF ,
|
||||
DATA_ACCESS_MASK5 : 36'h0FFFFFFFF ,
|
||||
DATA_ACCESS_MASK6 : 36'h0FFFFFFFF ,
|
||||
DATA_ACCESS_MASK7 : 36'h0FFFFFFFF ,
|
||||
DCCM_BANK_BITS : 7'h02 ,
|
||||
DCCM_BITS : 9'h010 ,
|
||||
DCCM_BYTE_WIDTH : 7'h04 ,
|
||||
DCCM_DATA_WIDTH : 10'h020 ,
|
||||
DCCM_ECC_WIDTH : 7'h07 ,
|
||||
DCCM_ENABLE : 5'h01 ,
|
||||
DCCM_FDATA_WIDTH : 10'h027 ,
|
||||
DCCM_INDEX_BITS : 8'h0C ,
|
||||
DCCM_NUM_BANKS : 9'h004 ,
|
||||
DCCM_REGION : 8'h0F ,
|
||||
DCCM_SADR : 36'h0F0040000 ,
|
||||
DCCM_SIZE : 14'h0040 ,
|
||||
DCCM_WIDTH_BITS : 6'h02 ,
|
||||
DIV_BIT : 7'h04 ,
|
||||
DIV_NEW : 5'h01 ,
|
||||
DMA_BUF_DEPTH : 7'h05 ,
|
||||
DMA_BUS_ID : 9'h001 ,
|
||||
DMA_BUS_PRTY : 6'h02 ,
|
||||
DMA_BUS_TAG : 8'h01 ,
|
||||
FAST_INTERRUPT_REDIRECT : 5'h01 ,
|
||||
ICACHE_2BANKS : 5'h01 ,
|
||||
ICACHE_BANK_BITS : 7'h01 ,
|
||||
ICACHE_BANK_HI : 7'h03 ,
|
||||
ICACHE_BANK_LO : 6'h03 ,
|
||||
ICACHE_BANK_WIDTH : 8'h08 ,
|
||||
ICACHE_BANKS_WAY : 7'h02 ,
|
||||
ICACHE_BEAT_ADDR_HI : 8'h05 ,
|
||||
ICACHE_BEAT_BITS : 8'h03 ,
|
||||
ICACHE_BYPASS_ENABLE : 5'h01 ,
|
||||
ICACHE_DATA_DEPTH : 18'h00200 ,
|
||||
ICACHE_DATA_INDEX_LO : 7'h04 ,
|
||||
ICACHE_DATA_WIDTH : 11'h040 ,
|
||||
ICACHE_ECC : 5'h01 ,
|
||||
ICACHE_ENABLE : 5'h01 ,
|
||||
ICACHE_FDATA_WIDTH : 11'h047 ,
|
||||
ICACHE_INDEX_HI : 9'h00C ,
|
||||
ICACHE_LN_SZ : 11'h040 ,
|
||||
ICACHE_NUM_BEATS : 8'h08 ,
|
||||
ICACHE_NUM_BYPASS : 8'h02 ,
|
||||
ICACHE_NUM_BYPASS_WIDTH : 8'h02 ,
|
||||
ICACHE_NUM_WAYS : 7'h02 ,
|
||||
ICACHE_ONLY : 5'h00 ,
|
||||
ICACHE_SCND_LAST : 8'h06 ,
|
||||
ICACHE_SIZE : 13'h0010 ,
|
||||
ICACHE_STATUS_BITS : 7'h01 ,
|
||||
ICACHE_TAG_BYPASS_ENABLE : 5'h01 ,
|
||||
ICACHE_TAG_DEPTH : 17'h00080 ,
|
||||
ICACHE_TAG_INDEX_LO : 7'h06 ,
|
||||
ICACHE_TAG_LO : 9'h00D ,
|
||||
ICACHE_TAG_NUM_BYPASS : 8'h02 ,
|
||||
ICACHE_TAG_NUM_BYPASS_WIDTH : 8'h02 ,
|
||||
ICACHE_WAYPACK : 5'h01 ,
|
||||
ICCM_BANK_BITS : 7'h02 ,
|
||||
ICCM_BANK_HI : 9'h003 ,
|
||||
ICCM_BANK_INDEX_LO : 9'h004 ,
|
||||
ICCM_BITS : 9'h010 ,
|
||||
ICCM_ENABLE : 5'h01 ,
|
||||
ICCM_ICACHE : 5'h01 ,
|
||||
ICCM_INDEX_BITS : 8'h0C ,
|
||||
ICCM_NUM_BANKS : 9'h004 ,
|
||||
ICCM_ONLY : 5'h00 ,
|
||||
ICCM_REGION : 8'h0E ,
|
||||
ICCM_SADR : 36'h0EE000000 ,
|
||||
ICCM_SIZE : 14'h0040 ,
|
||||
IFU_BUS_ID : 5'h01 ,
|
||||
IFU_BUS_PRTY : 6'h02 ,
|
||||
IFU_BUS_TAG : 8'h03 ,
|
||||
INST_ACCESS_ADDR0 : 36'h000000000 ,
|
||||
INST_ACCESS_ADDR1 : 36'h000000000 ,
|
||||
INST_ACCESS_ADDR2 : 36'h000000000 ,
|
||||
INST_ACCESS_ADDR3 : 36'h000000000 ,
|
||||
INST_ACCESS_ADDR4 : 36'h000000000 ,
|
||||
INST_ACCESS_ADDR5 : 36'h000000000 ,
|
||||
INST_ACCESS_ADDR6 : 36'h000000000 ,
|
||||
INST_ACCESS_ADDR7 : 36'h000000000 ,
|
||||
INST_ACCESS_ENABLE0 : 5'h00 ,
|
||||
INST_ACCESS_ENABLE1 : 5'h00 ,
|
||||
INST_ACCESS_ENABLE2 : 5'h00 ,
|
||||
INST_ACCESS_ENABLE3 : 5'h00 ,
|
||||
INST_ACCESS_ENABLE4 : 5'h00 ,
|
||||
INST_ACCESS_ENABLE5 : 5'h00 ,
|
||||
INST_ACCESS_ENABLE6 : 5'h00 ,
|
||||
INST_ACCESS_ENABLE7 : 5'h00 ,
|
||||
INST_ACCESS_MASK0 : 36'h0FFFFFFFF ,
|
||||
INST_ACCESS_MASK1 : 36'h0FFFFFFFF ,
|
||||
INST_ACCESS_MASK2 : 36'h0FFFFFFFF ,
|
||||
INST_ACCESS_MASK3 : 36'h0FFFFFFFF ,
|
||||
INST_ACCESS_MASK4 : 36'h0FFFFFFFF ,
|
||||
INST_ACCESS_MASK5 : 36'h0FFFFFFFF ,
|
||||
INST_ACCESS_MASK6 : 36'h0FFFFFFFF ,
|
||||
INST_ACCESS_MASK7 : 36'h0FFFFFFFF ,
|
||||
LOAD_TO_USE_PLUS1 : 5'h00 ,
|
||||
LSU2DMA : 5'h00 ,
|
||||
LSU_BUS_ID : 5'h01 ,
|
||||
LSU_BUS_PRTY : 6'h02 ,
|
||||
LSU_BUS_TAG : 8'h03 ,
|
||||
LSU_NUM_NBLOAD : 9'h004 ,
|
||||
LSU_NUM_NBLOAD_WIDTH : 7'h02 ,
|
||||
LSU_SB_BITS : 9'h010 ,
|
||||
LSU_STBUF_DEPTH : 8'h04 ,
|
||||
NO_ICCM_NO_ICACHE : 5'h00 ,
|
||||
PIC_2CYCLE : 5'h00 ,
|
||||
PIC_BASE_ADDR : 36'h0F00C0000 ,
|
||||
PIC_BITS : 9'h00F ,
|
||||
PIC_INT_WORDS : 8'h01 ,
|
||||
PIC_REGION : 8'h0F ,
|
||||
PIC_SIZE : 13'h0020 ,
|
||||
PIC_TOTAL_INT : 12'h01F ,
|
||||
PIC_TOTAL_INT_PLUS1 : 13'h0020 ,
|
||||
RET_STACK_SIZE : 8'h08 ,
|
||||
SB_BUS_ID : 5'h01 ,
|
||||
SB_BUS_PRTY : 6'h02 ,
|
||||
SB_BUS_TAG : 8'h01 ,
|
||||
TIMER_LEGAL_EN : 5'h01
|
||||
}
|
||||
// parameter el2_param_t pt = 2271'h04840400010040010840000020908200002840004808220A0C848200060210C00000000000000000000000000000000000000000000000000000000000000000000000000000000003FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC104020401C213860103C3C01000000400820428042010840830C2010281840200081002108E0C0801004040800C01002100400606810104100C0810084300800E0EE00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF8001080C080820080007806000003C043C04003E02008084021
|
||||
|
|
@ -1,175 +0,0 @@
|
|||
typedef struct packed {
|
||||
bit [7:0] BHT_ADDR_HI;
|
||||
bit [5:0] BHT_ADDR_LO;
|
||||
bit [14:0] BHT_ARRAY_DEPTH;
|
||||
bit [4:0] BHT_GHR_HASH_1;
|
||||
bit [7:0] BHT_GHR_SIZE;
|
||||
bit [15:0] BHT_SIZE;
|
||||
bit [4:0] BITMANIP_ZBA;
|
||||
bit [4:0] BITMANIP_ZBB;
|
||||
bit [4:0] BITMANIP_ZBC;
|
||||
bit [4:0] BITMANIP_ZBE;
|
||||
bit [4:0] BITMANIP_ZBF;
|
||||
bit [4:0] BITMANIP_ZBP;
|
||||
bit [4:0] BITMANIP_ZBR;
|
||||
bit [4:0] BITMANIP_ZBS;
|
||||
bit [8:0] BTB_ADDR_HI;
|
||||
bit [5:0] BTB_ADDR_LO;
|
||||
bit [12:0] BTB_ARRAY_DEPTH;
|
||||
bit [4:0] BTB_BTAG_FOLD;
|
||||
bit [8:0] BTB_BTAG_SIZE;
|
||||
bit [4:0] BTB_ENABLE;
|
||||
bit [4:0] BTB_FOLD2_INDEX_HASH;
|
||||
bit [4:0] BTB_FULLYA;
|
||||
bit [8:0] BTB_INDEX1_HI;
|
||||
bit [8:0] BTB_INDEX1_LO;
|
||||
bit [8:0] BTB_INDEX2_HI;
|
||||
bit [8:0] BTB_INDEX2_LO;
|
||||
bit [8:0] BTB_INDEX3_HI;
|
||||
bit [8:0] BTB_INDEX3_LO;
|
||||
bit [13:0] BTB_SIZE;
|
||||
bit [8:0] BTB_TOFFSET_SIZE;
|
||||
bit BUILD_AHB_LITE;
|
||||
bit [4:0] BUILD_AXI4;
|
||||
bit [4:0] BUILD_AXI_NATIVE;
|
||||
bit [5:0] BUS_PRTY_DEFAULT;
|
||||
bit [35:0] DATA_ACCESS_ADDR0;
|
||||
bit [35:0] DATA_ACCESS_ADDR1;
|
||||
bit [35:0] DATA_ACCESS_ADDR2;
|
||||
bit [35:0] DATA_ACCESS_ADDR3;
|
||||
bit [35:0] DATA_ACCESS_ADDR4;
|
||||
bit [35:0] DATA_ACCESS_ADDR5;
|
||||
bit [35:0] DATA_ACCESS_ADDR6;
|
||||
bit [35:0] DATA_ACCESS_ADDR7;
|
||||
bit [4:0] DATA_ACCESS_ENABLE0;
|
||||
bit [4:0] DATA_ACCESS_ENABLE1;
|
||||
bit [4:0] DATA_ACCESS_ENABLE2;
|
||||
bit [4:0] DATA_ACCESS_ENABLE3;
|
||||
bit [4:0] DATA_ACCESS_ENABLE4;
|
||||
bit [4:0] DATA_ACCESS_ENABLE5;
|
||||
bit [4:0] DATA_ACCESS_ENABLE6;
|
||||
bit [4:0] DATA_ACCESS_ENABLE7;
|
||||
bit [35:0] DATA_ACCESS_MASK0;
|
||||
bit [35:0] DATA_ACCESS_MASK1;
|
||||
bit [35:0] DATA_ACCESS_MASK2;
|
||||
bit [35:0] DATA_ACCESS_MASK3;
|
||||
bit [35:0] DATA_ACCESS_MASK4;
|
||||
bit [35:0] DATA_ACCESS_MASK5;
|
||||
bit [35:0] DATA_ACCESS_MASK6;
|
||||
bit [35:0] DATA_ACCESS_MASK7;
|
||||
bit [6:0] DCCM_BANK_BITS;
|
||||
bit [8:0] DCCM_BITS;
|
||||
bit [6:0] DCCM_BYTE_WIDTH;
|
||||
bit [9:0] DCCM_DATA_WIDTH;
|
||||
bit [6:0] DCCM_ECC_WIDTH;
|
||||
bit [4:0] DCCM_ENABLE;
|
||||
bit [9:0] DCCM_FDATA_WIDTH;
|
||||
bit [7:0] DCCM_INDEX_BITS;
|
||||
bit [8:0] DCCM_NUM_BANKS;
|
||||
bit [7:0] DCCM_REGION;
|
||||
bit [35:0] DCCM_SADR;
|
||||
bit [13:0] DCCM_SIZE;
|
||||
bit [5:0] DCCM_WIDTH_BITS;
|
||||
bit [6:0] DIV_BIT;
|
||||
bit [4:0] DIV_NEW;
|
||||
bit [6:0] DMA_BUF_DEPTH;
|
||||
bit [8:0] DMA_BUS_ID;
|
||||
bit [5:0] DMA_BUS_PRTY;
|
||||
bit [7:0] DMA_BUS_TAG;
|
||||
bit [4:0] FAST_INTERRUPT_REDIRECT;
|
||||
bit [4:0] ICACHE_2BANKS;
|
||||
bit [6:0] ICACHE_BANK_BITS;
|
||||
bit [6:0] ICACHE_BANK_HI;
|
||||
bit [5:0] ICACHE_BANK_LO;
|
||||
bit [7:0] ICACHE_BANK_WIDTH;
|
||||
bit [6:0] ICACHE_BANKS_WAY;
|
||||
bit [7:0] ICACHE_BEAT_ADDR_HI;
|
||||
bit [7:0] ICACHE_BEAT_BITS;
|
||||
bit [4:0] ICACHE_BYPASS_ENABLE;
|
||||
bit [17:0] ICACHE_DATA_DEPTH;
|
||||
bit [6:0] ICACHE_DATA_INDEX_LO;
|
||||
bit [10:0] ICACHE_DATA_WIDTH;
|
||||
bit [4:0] ICACHE_ECC;
|
||||
bit [4:0] ICACHE_ENABLE;
|
||||
bit [10:0] ICACHE_FDATA_WIDTH;
|
||||
bit [8:0] ICACHE_INDEX_HI;
|
||||
bit [10:0] ICACHE_LN_SZ;
|
||||
bit [7:0] ICACHE_NUM_BEATS;
|
||||
bit [7:0] ICACHE_NUM_BYPASS;
|
||||
bit [7:0] ICACHE_NUM_BYPASS_WIDTH;
|
||||
bit [6:0] ICACHE_NUM_WAYS;
|
||||
bit [4:0] ICACHE_ONLY;
|
||||
bit [7:0] ICACHE_SCND_LAST;
|
||||
bit [12:0] ICACHE_SIZE;
|
||||
bit [6:0] ICACHE_STATUS_BITS;
|
||||
bit [4:0] ICACHE_TAG_BYPASS_ENABLE;
|
||||
bit [16:0] ICACHE_TAG_DEPTH;
|
||||
bit [6:0] ICACHE_TAG_INDEX_LO;
|
||||
bit [8:0] ICACHE_TAG_LO;
|
||||
bit [7:0] ICACHE_TAG_NUM_BYPASS;
|
||||
bit [7:0] ICACHE_TAG_NUM_BYPASS_WIDTH;
|
||||
bit [4:0] ICACHE_WAYPACK;
|
||||
bit [6:0] ICCM_BANK_BITS;
|
||||
bit [8:0] ICCM_BANK_HI;
|
||||
bit [8:0] ICCM_BANK_INDEX_LO;
|
||||
bit [8:0] ICCM_BITS;
|
||||
bit [4:0] ICCM_ENABLE;
|
||||
bit [4:0] ICCM_ICACHE;
|
||||
bit [7:0] ICCM_INDEX_BITS;
|
||||
bit [8:0] ICCM_NUM_BANKS;
|
||||
bit [4:0] ICCM_ONLY;
|
||||
bit [7:0] ICCM_REGION;
|
||||
bit [35:0] ICCM_SADR;
|
||||
bit [13:0] ICCM_SIZE;
|
||||
bit [4:0] IFU_BUS_ID;
|
||||
bit [5:0] IFU_BUS_PRTY;
|
||||
bit [7:0] IFU_BUS_TAG;
|
||||
bit [35:0] INST_ACCESS_ADDR0;
|
||||
bit [35:0] INST_ACCESS_ADDR1;
|
||||
bit [35:0] INST_ACCESS_ADDR2;
|
||||
bit [35:0] INST_ACCESS_ADDR3;
|
||||
bit [35:0] INST_ACCESS_ADDR4;
|
||||
bit [35:0] INST_ACCESS_ADDR5;
|
||||
bit [35:0] INST_ACCESS_ADDR6;
|
||||
bit [35:0] INST_ACCESS_ADDR7;
|
||||
bit [4:0] INST_ACCESS_ENABLE0;
|
||||
bit [4:0] INST_ACCESS_ENABLE1;
|
||||
bit [4:0] INST_ACCESS_ENABLE2;
|
||||
bit [4:0] INST_ACCESS_ENABLE3;
|
||||
bit [4:0] INST_ACCESS_ENABLE4;
|
||||
bit [4:0] INST_ACCESS_ENABLE5;
|
||||
bit [4:0] INST_ACCESS_ENABLE6;
|
||||
bit [4:0] INST_ACCESS_ENABLE7;
|
||||
bit [35:0] INST_ACCESS_MASK0;
|
||||
bit [35:0] INST_ACCESS_MASK1;
|
||||
bit [35:0] INST_ACCESS_MASK2;
|
||||
bit [35:0] INST_ACCESS_MASK3;
|
||||
bit [35:0] INST_ACCESS_MASK4;
|
||||
bit [35:0] INST_ACCESS_MASK5;
|
||||
bit [35:0] INST_ACCESS_MASK6;
|
||||
bit [35:0] INST_ACCESS_MASK7;
|
||||
bit [4:0] LOAD_TO_USE_PLUS1;
|
||||
bit [4:0] LSU2DMA;
|
||||
bit [4:0] LSU_BUS_ID;
|
||||
bit [5:0] LSU_BUS_PRTY;
|
||||
bit [7:0] LSU_BUS_TAG;
|
||||
bit [8:0] LSU_NUM_NBLOAD;
|
||||
bit [6:0] LSU_NUM_NBLOAD_WIDTH;
|
||||
bit [8:0] LSU_SB_BITS;
|
||||
bit [7:0] LSU_STBUF_DEPTH;
|
||||
bit [4:0] NO_ICCM_NO_ICACHE;
|
||||
bit [4:0] PIC_2CYCLE;
|
||||
bit [35:0] PIC_BASE_ADDR;
|
||||
bit [8:0] PIC_BITS;
|
||||
bit [7:0] PIC_INT_WORDS;
|
||||
bit [7:0] PIC_REGION;
|
||||
bit [12:0] PIC_SIZE;
|
||||
bit [11:0] PIC_TOTAL_INT;
|
||||
bit [12:0] PIC_TOTAL_INT_PLUS1;
|
||||
bit [7:0] RET_STACK_SIZE;
|
||||
bit [4:0] SB_BUS_ID;
|
||||
bit [5:0] SB_BUS_PRTY;
|
||||
bit [7:0] SB_BUS_TAG;
|
||||
bit [4:0] TIMER_LEGAL_EN;
|
||||
} el2_param_t;
|
||||
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
/*
|
||||
NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
|
||||
This is an automatically generated file by colin on Mon Mar 7 04:09:03 AM UTC 2022
|
||||
|
||||
cmd: swerv -target=default -set build_axi4
|
||||
|
||||
*/
|
||||
OUTPUT_ARCH( "riscv" )
|
||||
ENTRY(_start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x80000000;
|
||||
.text.init . : { *(.text.init) }
|
||||
|
||||
.text . : { *(.text) }
|
||||
_end = .;
|
||||
. = 0xd0580000;
|
||||
.data.io . : { *(.data.io) }
|
||||
. = 0xf0040000 ;
|
||||
.data : ALIGN(0x800) { *(.*data) *(.rodata*)}
|
||||
.bss : {BSS_START = .; *(.*bss)}
|
||||
BSS_END = .;
|
||||
STACK = ALIGN(16) + 0x1000;
|
||||
|
||||
. = 0xfffffff8; .data.ctl : { LONG(0xf0040000); LONG(STACK) }
|
||||
}
|
||||
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
|
||||
// This is an automatically generated file by colin on Mon Mar 7 04:09:03 AM UTC 2022
|
||||
//
|
||||
// cmd: swerv -target=default -set build_axi4
|
||||
//
|
||||
|
||||
`include "common_defines.vh"
|
||||
`undef RV_ASSERT_ON
|
||||
`undef TEC_RV_ICG
|
||||
`define RV_PHYSICAL 1
|
||||
|
|
@ -1,778 +0,0 @@
|
|||
# NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
|
||||
# This is an automatically generated file by colin on Mon Mar 7 04:09:03 AM UTC 2022
|
||||
#
|
||||
# cmd: swerv -target=default -set build_axi4
|
||||
#
|
||||
# To use this in a perf script, use 'require $RV_ROOT/configs/config.pl'
|
||||
# Reference the hash via $config{name}..
|
||||
|
||||
|
||||
%config = (
|
||||
'nmi_vec' => '0x11110000',
|
||||
'numiregs' => '32',
|
||||
'perf_events' => [
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
30,
|
||||
31,
|
||||
32,
|
||||
34,
|
||||
35,
|
||||
36,
|
||||
37,
|
||||
38,
|
||||
39,
|
||||
40,
|
||||
41,
|
||||
42,
|
||||
43,
|
||||
44,
|
||||
45,
|
||||
46,
|
||||
47,
|
||||
48,
|
||||
49,
|
||||
50,
|
||||
54,
|
||||
55,
|
||||
56,
|
||||
512,
|
||||
513,
|
||||
514,
|
||||
515,
|
||||
516
|
||||
],
|
||||
'bht' => {
|
||||
'bht_ghr_range' => '7:0',
|
||||
'bht_hash_string' => '{hashin[8+1:2]^ghr[8-1:0]}// cf2',
|
||||
'bht_addr_hi' => 9,
|
||||
'bht_ghr_size' => 8,
|
||||
'bht_array_depth' => 256,
|
||||
'bht_ghr_hash_1' => '',
|
||||
'bht_size' => 512,
|
||||
'bht_addr_lo' => '2'
|
||||
},
|
||||
'retstack' => {
|
||||
'ret_stack_size' => '8'
|
||||
},
|
||||
'config_key' => '32\'hdeadbeef',
|
||||
'even_odd_trigger_chains' => 'true',
|
||||
'target' => 'default',
|
||||
'dccm' => {
|
||||
'dccm_offset' => '0x40000',
|
||||
'dccm_region' => '0xf',
|
||||
'dccm_eadr' => '0xf004ffff',
|
||||
'dccm_size' => 64,
|
||||
'dccm_sadr' => '0xf0040000',
|
||||
'dccm_fdata_width' => 39,
|
||||
'dccm_bank_bits' => 2,
|
||||
'dccm_num_banks_4' => '',
|
||||
'dccm_rows' => '4096',
|
||||
'dccm_enable' => '1',
|
||||
'dccm_index_bits' => 12,
|
||||
'dccm_bits' => 16,
|
||||
'dccm_num_banks' => '4',
|
||||
'lsu_sb_bits' => 16,
|
||||
'dccm_data_width' => 32,
|
||||
'dccm_data_cell' => 'ram_4096x39',
|
||||
'dccm_reserved' => '0x1400',
|
||||
'dccm_size_64' => '',
|
||||
'dccm_ecc_width' => 7,
|
||||
'dccm_width_bits' => 2,
|
||||
'dccm_byte_width' => '4'
|
||||
},
|
||||
'max_mmode_perf_event' => '516',
|
||||
'regwidth' => '32',
|
||||
'reset_vec' => '0x80000000',
|
||||
'core' => {
|
||||
'lsu_stbuf_depth' => '4',
|
||||
'bitmanip_zbr' => 0,
|
||||
'bitmanip_zbs' => 1,
|
||||
'bitmanip_zbf' => 0,
|
||||
'fpga_optimize' => 1,
|
||||
'icache_only' => 'derived',
|
||||
'dma_buf_depth' => '5',
|
||||
'bitmanip_zbc' => 1,
|
||||
'bitmanip_zbe' => 0,
|
||||
'iccm_icache' => 1,
|
||||
'fast_interrupt_redirect' => '1',
|
||||
'lsu_num_nbload' => '4',
|
||||
'iccm_only' => 'derived',
|
||||
'bitmanip_zba' => 1,
|
||||
'bitmanip_zbp' => 0,
|
||||
'lsu2dma' => 0,
|
||||
'lsu_num_nbload_width' => '2',
|
||||
'div_bit' => '4',
|
||||
'bitmanip_zbb' => 1,
|
||||
'no_iccm_no_icache' => 'derived',
|
||||
'timer_legal_en' => '1',
|
||||
'div_new' => 1
|
||||
},
|
||||
'memmap' => {
|
||||
'unused_region8' => '0x00000000',
|
||||
'unused_region2' => '0x60000000',
|
||||
'unused_region1' => '0x70000000',
|
||||
'unused_region5' => '0x30000000',
|
||||
'unused_region4' => '0x40000000',
|
||||
'serialio' => '0xd0580000',
|
||||
'external_data' => '0xc0580000',
|
||||
'external_data_1' => '0xb0000000',
|
||||
'unused_region0' => '0x90000000',
|
||||
'unused_region3' => '0x50000000',
|
||||
'consoleio' => '0xd0580000',
|
||||
'unused_region7' => '0x10000000',
|
||||
'debug_sb_mem' => '0xa0580000',
|
||||
'unused_region6' => '0x20000000'
|
||||
},
|
||||
'iccm' => {
|
||||
'iccm_num_banks' => '4',
|
||||
'iccm_bits' => 16,
|
||||
'iccm_index_bits' => 12,
|
||||
'iccm_enable' => 1,
|
||||
'iccm_size_64' => '',
|
||||
'iccm_data_cell' => 'ram_4096x39',
|
||||
'iccm_reserved' => '0x1000',
|
||||
'iccm_bank_index_lo' => 4,
|
||||
'iccm_sadr' => '0xee000000',
|
||||
'iccm_eadr' => '0xee00ffff',
|
||||
'iccm_offset' => '0xe000000',
|
||||
'iccm_region' => '0xe',
|
||||
'iccm_size' => 64,
|
||||
'iccm_num_banks_4' => '',
|
||||
'iccm_rows' => '4096',
|
||||
'iccm_bank_hi' => 3,
|
||||
'iccm_bank_bits' => 2
|
||||
},
|
||||
'pic' => {
|
||||
'pic_meipl_mask' => '0xf',
|
||||
'pic_meipl_count' => 31,
|
||||
'pic_meie_count' => 31,
|
||||
'pic_meip_mask' => '0x0',
|
||||
'pic_meipt_offset' => '0x3004',
|
||||
'pic_region' => '0xf',
|
||||
'pic_total_int' => 31,
|
||||
'pic_meigwctrl_offset' => '0x4000',
|
||||
'pic_meip_count' => 1,
|
||||
'pic_meie_mask' => '0x1',
|
||||
'pic_mpiccfg_offset' => '0x3000',
|
||||
'pic_meigwclr_mask' => '0x0',
|
||||
'pic_meigwclr_count' => 31,
|
||||
'pic_int_words' => 1,
|
||||
'pic_offset' => '0xc0000',
|
||||
'pic_meip_offset' => '0x1000',
|
||||
'pic_bits' => 15,
|
||||
'pic_mpiccfg_count' => 1,
|
||||
'pic_meigwclr_offset' => '0x5000',
|
||||
'pic_size' => 32,
|
||||
'pic_mpiccfg_mask' => '0x1',
|
||||
'pic_total_int_plus1' => 32,
|
||||
'pic_meipl_offset' => '0x0000',
|
||||
'pic_meigwctrl_count' => 31,
|
||||
'pic_base_addr' => '0xf00c0000',
|
||||
'pic_meipt_mask' => '0x0',
|
||||
'pic_meie_offset' => '0x2000',
|
||||
'pic_meigwctrl_mask' => '0x3',
|
||||
'pic_meipt_count' => 31
|
||||
},
|
||||
'protection' => {
|
||||
'inst_access_addr2' => '0x00000000',
|
||||
'data_access_mask6' => '0xffffffff',
|
||||
'data_access_enable0' => '0x0',
|
||||
'inst_access_enable4' => '0x0',
|
||||
'inst_access_mask1' => '0xffffffff',
|
||||
'inst_access_addr5' => '0x00000000',
|
||||
'inst_access_enable1' => '0x0',
|
||||
'inst_access_mask4' => '0xffffffff',
|
||||
'data_access_addr2' => '0x00000000',
|
||||
'inst_access_mask6' => '0xffffffff',
|
||||
'inst_access_enable0' => '0x0',
|
||||
'data_access_addr5' => '0x00000000',
|
||||
'data_access_mask1' => '0xffffffff',
|
||||
'data_access_enable4' => '0x0',
|
||||
'data_access_enable1' => '0x0',
|
||||
'data_access_mask4' => '0xffffffff',
|
||||
'data_access_enable6' => '0x0',
|
||||
'inst_access_mask7' => '0xffffffff',
|
||||
'inst_access_enable5' => '0x0',
|
||||
'data_access_mask0' => '0xffffffff',
|
||||
'inst_access_addr3' => '0x00000000',
|
||||
'inst_access_enable6' => '0x0',
|
||||
'data_access_mask7' => '0xffffffff',
|
||||
'data_access_enable5' => '0x0',
|
||||
'inst_access_mask0' => '0xffffffff',
|
||||
'data_access_addr3' => '0x00000000',
|
||||
'data_access_enable3' => '0x0',
|
||||
'data_access_addr0' => '0x00000000',
|
||||
'inst_access_mask3' => '0xffffffff',
|
||||
'data_access_enable2' => '0x0',
|
||||
'inst_access_addr7' => '0x00000000',
|
||||
'inst_access_enable3' => '0x0',
|
||||
'inst_access_addr0' => '0x00000000',
|
||||
'data_access_mask3' => '0xffffffff',
|
||||
'data_access_addr7' => '0x00000000',
|
||||
'inst_access_enable2' => '0x0',
|
||||
'inst_access_mask5' => '0xffffffff',
|
||||
'inst_access_addr1' => '0x00000000',
|
||||
'inst_access_addr4' => '0x00000000',
|
||||
'inst_access_mask2' => '0xffffffff',
|
||||
'inst_access_enable7' => '0x0',
|
||||
'data_access_addr6' => '0x00000000',
|
||||
'data_access_addr1' => '0x00000000',
|
||||
'data_access_mask5' => '0xffffffff',
|
||||
'data_access_addr4' => '0x00000000',
|
||||
'data_access_mask2' => '0xffffffff',
|
||||
'data_access_enable7' => '0x0',
|
||||
'inst_access_addr6' => '0x00000000'
|
||||
},
|
||||
'physical' => '1',
|
||||
'bus' => {
|
||||
'ifu_bus_prty' => '2',
|
||||
'sb_bus_prty' => '2',
|
||||
'lsu_bus_id' => '1',
|
||||
'lsu_bus_tag' => 3,
|
||||
'sb_bus_tag' => '1',
|
||||
'dma_bus_id' => '1',
|
||||
'dma_bus_tag' => '1',
|
||||
'lsu_bus_prty' => '2',
|
||||
'bus_prty_default' => '3',
|
||||
'sb_bus_id' => '1',
|
||||
'dma_bus_prty' => '2',
|
||||
'ifu_bus_id' => '1',
|
||||
'ifu_bus_tag' => '3'
|
||||
},
|
||||
'harts' => 1,
|
||||
'xlen' => 32,
|
||||
'btb' => {
|
||||
'btb_index3_lo' => 18,
|
||||
'btb_index1_lo' => '2',
|
||||
'btb_addr_hi' => 9,
|
||||
'btb_index2_lo' => 10,
|
||||
'btb_size' => 512,
|
||||
'btb_btag_fold' => 0,
|
||||
'btb_addr_lo' => '2',
|
||||
'btb_index2_hi' => 17,
|
||||
'btb_enable' => '1',
|
||||
'btb_toffset_size' => '12',
|
||||
'btb_index3_hi' => 25,
|
||||
'btb_array_depth' => 256,
|
||||
'btb_btag_size' => 5,
|
||||
'btb_index1_hi' => 9,
|
||||
'btb_fold2_index_hash' => 0
|
||||
},
|
||||
'tec_rv_icg' => 'clockhdr',
|
||||
'triggers' => [
|
||||
{
|
||||
'poke_mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'reset' => [
|
||||
'0x23e00000',
|
||||
'0x00000000',
|
||||
'0x00000000'
|
||||
]
|
||||
},
|
||||
{
|
||||
'poke_mask' => [
|
||||
'0x081810c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'mask' => [
|
||||
'0x081810c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'reset' => [
|
||||
'0x23e00000',
|
||||
'0x00000000',
|
||||
'0x00000000'
|
||||
]
|
||||
},
|
||||
{
|
||||
'reset' => [
|
||||
'0x23e00000',
|
||||
'0x00000000',
|
||||
'0x00000000'
|
||||
],
|
||||
'poke_mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'mask' => [
|
||||
'0x081818c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
]
|
||||
},
|
||||
{
|
||||
'poke_mask' => [
|
||||
'0x081810c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'mask' => [
|
||||
'0x081810c7',
|
||||
'0xffffffff',
|
||||
'0x00000000'
|
||||
],
|
||||
'reset' => [
|
||||
'0x23e00000',
|
||||
'0x00000000',
|
||||
'0x00000000'
|
||||
]
|
||||
}
|
||||
],
|
||||
'num_mmode_perf_regs' => '4',
|
||||
'testbench' => {
|
||||
'assert_on' => '',
|
||||
'sterr_rollback' => '0',
|
||||
'build_axi4' => 1,
|
||||
'SDVT_AHB' => '0',
|
||||
'ext_datawidth' => '64',
|
||||
'ext_addrwidth' => '32',
|
||||
'TOP' => 'tb_top',
|
||||
'lderr_rollback' => '1',
|
||||
'build_axi_native' => 1,
|
||||
'RV_TOP' => '`TOP.rvtop',
|
||||
'clock_period' => '100',
|
||||
'CPU_TOP' => '`RV_TOP.swerv'
|
||||
},
|
||||
'icache' => {
|
||||
'icache_index_hi' => 12,
|
||||
'icache_tag_cell' => 'ram_128x25',
|
||||
'icache_num_beats' => 8,
|
||||
'icache_fdata_width' => 71,
|
||||
'icache_num_bypass_width' => 2,
|
||||
'icache_tag_depth' => 128,
|
||||
'icache_tag_bypass_enable' => '1',
|
||||
'icache_size' => 16,
|
||||
'icache_tag_num_bypass' => '2',
|
||||
'icache_bank_width' => 8,
|
||||
'icache_data_index_lo' => 4,
|
||||
'icache_2banks' => '1',
|
||||
'icache_num_lines_bank' => '64',
|
||||
'icache_ecc' => '1',
|
||||
'icache_status_bits' => 1,
|
||||
'icache_tag_num_bypass_width' => 2,
|
||||
'icache_beat_bits' => 3,
|
||||
'icache_data_width' => 64,
|
||||
'icache_bypass_enable' => '1',
|
||||
'icache_waypack' => '1',
|
||||
'icache_num_bypass' => '2',
|
||||
'icache_data_depth' => '512',
|
||||
'icache_beat_addr_hi' => 5,
|
||||
'icache_tag_lo' => 13,
|
||||
'icache_bank_bits' => 1,
|
||||
'icache_enable' => 1,
|
||||
'icache_bank_hi' => 3,
|
||||
'icache_num_lines' => 256,
|
||||
'icache_tag_index_lo' => '6',
|
||||
'icache_ln_sz' => 64,
|
||||
'icache_num_lines_way' => '128',
|
||||
'icache_data_cell' => 'ram_512x71',
|
||||
'icache_banks_way' => 2,
|
||||
'icache_num_ways' => 2,
|
||||
'icache_scnd_last' => 6,
|
||||
'icache_bank_lo' => 3
|
||||
},
|
||||
'csr' => {
|
||||
'mip' => {
|
||||
'exists' => 'true',
|
||||
'mask' => '0x0',
|
||||
'poke_mask' => '0x70000888',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'mscause' => {
|
||||
'mask' => '0x0000000f',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true',
|
||||
'number' => '0x7ff'
|
||||
},
|
||||
'micect' => {
|
||||
'exists' => 'true',
|
||||
'number' => '0x7f0',
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'pmpaddr12' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'dicago' => {
|
||||
'number' => '0x7cb',
|
||||
'exists' => 'true',
|
||||
'debug' => 'true',
|
||||
'comment' => 'Cache diagnostics.',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0x0'
|
||||
},
|
||||
'mrac' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'comment' => 'Memory region io and cache control.',
|
||||
'mask' => '0xffffffff',
|
||||
'number' => '0x7c0',
|
||||
'shared' => 'true'
|
||||
},
|
||||
'tselect' => {
|
||||
'mask' => '0x3',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'mhpmcounter4' => {
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'pmpcfg1' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr11' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mimpid' => {
|
||||
'mask' => '0x0',
|
||||
'reset' => '0x4',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'pmpaddr2' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mhpmevent6' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'cycle' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mitcnt1' => {
|
||||
'number' => '0x7d5',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'mcpc' => {
|
||||
'number' => '0x7c2',
|
||||
'exists' => 'true',
|
||||
'mask' => '0x0',
|
||||
'comment' => 'Core pause',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'pmpaddr6' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr1' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mhpmevent3' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'mdccmect' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0',
|
||||
'number' => '0x7f2',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'mitbnd0' => {
|
||||
'number' => '0x7d3',
|
||||
'exists' => 'true',
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0xffffffff'
|
||||
},
|
||||
'instret' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr14' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mvendorid' => {
|
||||
'exists' => 'true',
|
||||
'mask' => '0x0',
|
||||
'reset' => '0x45'
|
||||
},
|
||||
'mhpmcounter3' => {
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'mfdhs' => {
|
||||
'mask' => '0x00000003',
|
||||
'comment' => 'Force Debug Halt Status',
|
||||
'reset' => '0x0',
|
||||
'number' => '0x7cf',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'dicad1' => {
|
||||
'number' => '0x7ca',
|
||||
'exists' => 'true',
|
||||
'debug' => 'true',
|
||||
'comment' => 'Cache diagnostics.',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0x3'
|
||||
},
|
||||
'pmpcfg2' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mhpmcounter4h' => {
|
||||
'exists' => 'true',
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'mfdht' => {
|
||||
'number' => '0x7ce',
|
||||
'shared' => 'true',
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'comment' => 'Force Debug Halt Threshold',
|
||||
'mask' => '0x0000003f'
|
||||
},
|
||||
'pmpaddr13' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mhpmevent4' => {
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'mitctl1' => {
|
||||
'mask' => '0x0000000f',
|
||||
'reset' => '0x1',
|
||||
'exists' => 'true',
|
||||
'number' => '0x7d7'
|
||||
},
|
||||
'pmpaddr4' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mie' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0x70000888'
|
||||
},
|
||||
'mfdc' => {
|
||||
'number' => '0x7f9',
|
||||
'exists' => 'true',
|
||||
'mask' => '0x00071fff',
|
||||
'reset' => '0x00070040'
|
||||
},
|
||||
'pmpaddr9' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr0' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mpmc' => {
|
||||
'exists' => 'true',
|
||||
'number' => '0x7c6',
|
||||
'reset' => '0x2',
|
||||
'mask' => '0x2'
|
||||
},
|
||||
'pmpaddr3' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'marchid' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x00000010',
|
||||
'mask' => '0x0'
|
||||
},
|
||||
'meicidpl' => {
|
||||
'comment' => 'External interrupt claim id priority level.',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xf',
|
||||
'number' => '0xbcb',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'mhpmcounter3h' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'dmst' => {
|
||||
'exists' => 'true',
|
||||
'number' => '0x7c4',
|
||||
'debug' => 'true',
|
||||
'reset' => '0x0',
|
||||
'comment' => 'Memory synch trigger: Flush caches in debug mode.',
|
||||
'mask' => '0x0'
|
||||
},
|
||||
'mstatus' => {
|
||||
'exists' => 'true',
|
||||
'mask' => '0x88',
|
||||
'reset' => '0x1800'
|
||||
},
|
||||
'dicad0' => {
|
||||
'debug' => 'true',
|
||||
'exists' => 'true',
|
||||
'number' => '0x7c9',
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0',
|
||||
'comment' => 'Cache diagnostics.'
|
||||
},
|
||||
'mcgc' => {
|
||||
'reset' => '0x200',
|
||||
'poke_mask' => '0x000003ff',
|
||||
'mask' => '0x000003ff',
|
||||
'number' => '0x7f8',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'mhpmcounter5' => {
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'mhpmcounter6h' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'mcounteren' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'misa' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x40001104',
|
||||
'mask' => '0x0'
|
||||
},
|
||||
'pmpcfg0' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mcountinhibit' => {
|
||||
'commnet' => 'Performance counter inhibit. One bit per counter.',
|
||||
'exists' => 'true',
|
||||
'poke_mask' => '0x7d',
|
||||
'mask' => '0x7d',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'dcsr' => {
|
||||
'debug' => 'true',
|
||||
'exists' => 'true',
|
||||
'mask' => '0x00008c04',
|
||||
'poke_mask' => '0x00008dcc',
|
||||
'reset' => '0x40000003'
|
||||
},
|
||||
'time' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mhpmevent5' => {
|
||||
'exists' => 'true',
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'pmpaddr8' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpcfg3' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mitbnd1' => {
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0xffffffff',
|
||||
'exists' => 'true',
|
||||
'number' => '0x7d6'
|
||||
},
|
||||
'mitcnt0' => {
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff',
|
||||
'number' => '0x7d2',
|
||||
'exists' => 'true'
|
||||
},
|
||||
'miccmect' => {
|
||||
'exists' => 'true',
|
||||
'number' => '0x7f1',
|
||||
'mask' => '0xffffffff',
|
||||
'reset' => '0x0'
|
||||
},
|
||||
'mhpmcounter6' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'mhpmcounter5h' => {
|
||||
'exists' => 'true',
|
||||
'reset' => '0x0',
|
||||
'mask' => '0xffffffff'
|
||||
},
|
||||
'pmpaddr7' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'pmpaddr5' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'mitctl0' => {
|
||||
'number' => '0x7d4',
|
||||
'exists' => 'true',
|
||||
'mask' => '0x00000007',
|
||||
'reset' => '0x1'
|
||||
},
|
||||
'meicurpl' => {
|
||||
'exists' => 'true',
|
||||
'number' => '0xbcc',
|
||||
'reset' => '0x0',
|
||||
'comment' => 'External interrupt current priority level.',
|
||||
'mask' => '0xf'
|
||||
},
|
||||
'pmpaddr10' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'meipt' => {
|
||||
'exists' => 'true',
|
||||
'number' => '0xbc9',
|
||||
'reset' => '0x0',
|
||||
'comment' => 'External interrupt priority threshold.',
|
||||
'mask' => '0xf'
|
||||
},
|
||||
'pmpaddr15' => {
|
||||
'exists' => 'false'
|
||||
},
|
||||
'dicawics' => {
|
||||
'mask' => '0x0130fffc',
|
||||
'reset' => '0x0',
|
||||
'comment' => 'Cache diagnostics.',
|
||||
'debug' => 'true',
|
||||
'exists' => 'true',
|
||||
'number' => '0x7c8'
|
||||
},
|
||||
'mhartid' => {
|
||||
'exists' => 'true',
|
||||
'mask' => '0x0',
|
||||
'poke_mask' => '0xfffffff0',
|
||||
'reset' => '0x0'
|
||||
}
|
||||
}
|
||||
);
|
||||
1;
|
||||
|
|
@ -1,100 +0,0 @@
|
|||
// mask[3:0] = { 4'b1000 - 30b mask,4'b0100 - 31b mask, 4'b0010 - 28b mask, 4'b0001 - 32b mask }
|
||||
always_comb begin
|
||||
case (address[14:0])
|
||||
15'b011000000000000 : mask[3:0] = 4'b0100;
|
||||
15'b100000000000100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000001000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000001100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000010000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000010100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000011000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000011100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000100000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000100100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000101000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000101100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000110000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000110100 : mask[3:0] = 4'b1000;
|
||||
15'b100000000111000 : mask[3:0] = 4'b1000;
|
||||
15'b100000000111100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001000000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001000100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001001000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001001100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001010000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001010100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001011000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001011100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001100000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001100100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001101000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001101100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001110000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001110100 : mask[3:0] = 4'b1000;
|
||||
15'b100000001111000 : mask[3:0] = 4'b1000;
|
||||
15'b100000001111100 : mask[3:0] = 4'b1000;
|
||||
15'b010000000000100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000001000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000001100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000010000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000010100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000011000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000011100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000100000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000100100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000101000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000101100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000110000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000110100 : mask[3:0] = 4'b0100;
|
||||
15'b010000000111000 : mask[3:0] = 4'b0100;
|
||||
15'b010000000111100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001000000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001000100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001001000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001001100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001010000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001010100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001011000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001011100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001100000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001100100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001101000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001101100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001110000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001110100 : mask[3:0] = 4'b0100;
|
||||
15'b010000001111000 : mask[3:0] = 4'b0100;
|
||||
15'b010000001111100 : mask[3:0] = 4'b0100;
|
||||
15'b000000000000100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000001000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000001100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000010000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000010100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000011000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000011100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000100000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000100100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000101000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000101100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000110000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000110100 : mask[3:0] = 4'b0010;
|
||||
15'b000000000111000 : mask[3:0] = 4'b0010;
|
||||
15'b000000000111100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001000000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001000100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001001000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001001100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001010000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001010100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001011000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001011100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001100000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001100100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001101000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001101100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001110000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001110100 : mask[3:0] = 4'b0010;
|
||||
15'b000000001111000 : mask[3:0] = 4'b0010;
|
||||
15'b000000001111100 : mask[3:0] = 4'b0010;
|
||||
default : mask[3:0] = 4'b0001;
|
||||
endcase
|
||||
end
|
||||
|
|
@ -1,566 +0,0 @@
|
|||
{
|
||||
"enable_zbs" : 1,
|
||||
"nmi_vec" : "0x11110000",
|
||||
"enable_zbc" : 1,
|
||||
"effective_address_compatible_with_base" : "true",
|
||||
"mmode_perf_events" : [
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
30,
|
||||
31,
|
||||
32,
|
||||
34,
|
||||
35,
|
||||
36,
|
||||
37,
|
||||
38,
|
||||
39,
|
||||
40,
|
||||
41,
|
||||
42,
|
||||
43,
|
||||
44,
|
||||
45,
|
||||
46,
|
||||
47,
|
||||
48,
|
||||
49,
|
||||
50,
|
||||
54,
|
||||
55,
|
||||
56,
|
||||
512,
|
||||
513,
|
||||
514,
|
||||
515,
|
||||
516
|
||||
],
|
||||
"even_odd_trigger_chains" : "true",
|
||||
"max_mmode_perf_event" : "516",
|
||||
"dccm" : {
|
||||
"offset" : "0x40000",
|
||||
"size" : "0x10000",
|
||||
"region" : "0xf"
|
||||
},
|
||||
"reset_vec" : "0x80000000",
|
||||
"enable_zbp" : 0,
|
||||
"enable_zbb" : 1,
|
||||
"store_error_rollback" : "0",
|
||||
"memmap" : {
|
||||
"serialio" : "0xd0580000",
|
||||
"consoleio" : "0xd0580000"
|
||||
},
|
||||
"harts" : 1,
|
||||
"xlen" : 32,
|
||||
"enable_zbe" : 0,
|
||||
"enable_zbr" : 0,
|
||||
"amo_illegal_outside_dccm" : "true",
|
||||
"iccm" : {
|
||||
"region" : "0xe",
|
||||
"size" : "0x10000",
|
||||
"offset" : "0xe000000"
|
||||
},
|
||||
"enable_zba" : 1,
|
||||
"num_mmode_perf_regs" : "4",
|
||||
"enable_zbf" : 0,
|
||||
"load_error_rollback" : "1",
|
||||
"triggers" : [
|
||||
{
|
||||
"poke_mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"reset" : [
|
||||
"0x23e00000",
|
||||
"0x00000000",
|
||||
"0x00000000"
|
||||
]
|
||||
},
|
||||
{
|
||||
"poke_mask" : [
|
||||
"0x081810c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"mask" : [
|
||||
"0x081810c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"reset" : [
|
||||
"0x23e00000",
|
||||
"0x00000000",
|
||||
"0x00000000"
|
||||
]
|
||||
},
|
||||
{
|
||||
"reset" : [
|
||||
"0x23e00000",
|
||||
"0x00000000",
|
||||
"0x00000000"
|
||||
],
|
||||
"poke_mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"mask" : [
|
||||
"0x081818c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
]
|
||||
},
|
||||
{
|
||||
"poke_mask" : [
|
||||
"0x081810c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"mask" : [
|
||||
"0x081810c7",
|
||||
"0xffffffff",
|
||||
"0x00000000"
|
||||
],
|
||||
"reset" : [
|
||||
"0x23e00000",
|
||||
"0x00000000",
|
||||
"0x00000000"
|
||||
]
|
||||
}
|
||||
],
|
||||
"fast_interrupt_redirect" : "1",
|
||||
"csr" : {
|
||||
"mip" : {
|
||||
"exists" : "true",
|
||||
"mask" : "0x0",
|
||||
"poke_mask" : "0x70000888",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"mscause" : {
|
||||
"mask" : "0x0000000f",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true",
|
||||
"number" : "0x7ff"
|
||||
},
|
||||
"micect" : {
|
||||
"exists" : "true",
|
||||
"number" : "0x7f0",
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"pmpaddr12" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"dicago" : {
|
||||
"number" : "0x7cb",
|
||||
"exists" : "true",
|
||||
"debug" : "true",
|
||||
"comment" : "Cache diagnostics.",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0x0"
|
||||
},
|
||||
"mrac" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"comment" : "Memory region io and cache control.",
|
||||
"mask" : "0xffffffff",
|
||||
"number" : "0x7c0",
|
||||
"shared" : "true"
|
||||
},
|
||||
"tselect" : {
|
||||
"mask" : "0x3",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true"
|
||||
},
|
||||
"mhpmcounter4" : {
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff",
|
||||
"exists" : "true"
|
||||
},
|
||||
"pmpcfg1" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr11" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mimpid" : {
|
||||
"mask" : "0x0",
|
||||
"reset" : "0x4",
|
||||
"exists" : "true"
|
||||
},
|
||||
"pmpaddr2" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mhpmevent6" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"cycle" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mitcnt1" : {
|
||||
"number" : "0x7d5",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"mcpc" : {
|
||||
"number" : "0x7c2",
|
||||
"exists" : "true",
|
||||
"mask" : "0x0",
|
||||
"comment" : "Core pause",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"pmpaddr6" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr1" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mhpmevent3" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0",
|
||||
"exists" : "true"
|
||||
},
|
||||
"mdccmect" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0",
|
||||
"number" : "0x7f2",
|
||||
"exists" : "true"
|
||||
},
|
||||
"mitbnd0" : {
|
||||
"number" : "0x7d3",
|
||||
"exists" : "true",
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0xffffffff"
|
||||
},
|
||||
"instret" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr14" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mvendorid" : {
|
||||
"exists" : "true",
|
||||
"mask" : "0x0",
|
||||
"reset" : "0x45"
|
||||
},
|
||||
"mhpmcounter3" : {
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff",
|
||||
"exists" : "true"
|
||||
},
|
||||
"mfdhs" : {
|
||||
"mask" : "0x00000003",
|
||||
"comment" : "Force Debug Halt Status",
|
||||
"reset" : "0x0",
|
||||
"number" : "0x7cf",
|
||||
"exists" : "true"
|
||||
},
|
||||
"dicad1" : {
|
||||
"number" : "0x7ca",
|
||||
"exists" : "true",
|
||||
"debug" : "true",
|
||||
"comment" : "Cache diagnostics.",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0x3"
|
||||
},
|
||||
"pmpcfg2" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mhpmcounter4h" : {
|
||||
"exists" : "true",
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"mfdht" : {
|
||||
"number" : "0x7ce",
|
||||
"shared" : "true",
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"comment" : "Force Debug Halt Threshold",
|
||||
"mask" : "0x0000003f"
|
||||
},
|
||||
"pmpaddr13" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mhpmevent4" : {
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff",
|
||||
"exists" : "true"
|
||||
},
|
||||
"mitctl1" : {
|
||||
"mask" : "0x0000000f",
|
||||
"reset" : "0x1",
|
||||
"exists" : "true",
|
||||
"number" : "0x7d7"
|
||||
},
|
||||
"pmpaddr4" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mie" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0x70000888"
|
||||
},
|
||||
"mfdc" : {
|
||||
"number" : "0x7f9",
|
||||
"exists" : "true",
|
||||
"mask" : "0x00071fff",
|
||||
"reset" : "0x00070040"
|
||||
},
|
||||
"pmpaddr9" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr0" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mpmc" : {
|
||||
"exists" : "true",
|
||||
"number" : "0x7c6",
|
||||
"reset" : "0x2",
|
||||
"mask" : "0x2"
|
||||
},
|
||||
"pmpaddr3" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"marchid" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x00000010",
|
||||
"mask" : "0x0"
|
||||
},
|
||||
"meicidpl" : {
|
||||
"comment" : "External interrupt claim id priority level.",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xf",
|
||||
"number" : "0xbcb",
|
||||
"exists" : "true"
|
||||
},
|
||||
"mhpmcounter3h" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"dmst" : {
|
||||
"exists" : "true",
|
||||
"number" : "0x7c4",
|
||||
"debug" : "true",
|
||||
"reset" : "0x0",
|
||||
"comment" : "Memory synch trigger: Flush caches in debug mode.",
|
||||
"mask" : "0x0"
|
||||
},
|
||||
"mstatus" : {
|
||||
"exists" : "true",
|
||||
"mask" : "0x88",
|
||||
"reset" : "0x1800"
|
||||
},
|
||||
"dicad0" : {
|
||||
"debug" : "true",
|
||||
"exists" : "true",
|
||||
"number" : "0x7c9",
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0",
|
||||
"comment" : "Cache diagnostics."
|
||||
},
|
||||
"mcgc" : {
|
||||
"reset" : "0x200",
|
||||
"poke_mask" : "0x000003ff",
|
||||
"mask" : "0x000003ff",
|
||||
"number" : "0x7f8",
|
||||
"exists" : "true"
|
||||
},
|
||||
"mhpmcounter5" : {
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff",
|
||||
"exists" : "true"
|
||||
},
|
||||
"mhpmcounter6h" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"mcounteren" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"misa" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x40001104",
|
||||
"mask" : "0x0"
|
||||
},
|
||||
"pmpcfg0" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mcountinhibit" : {
|
||||
"commnet" : "Performance counter inhibit. One bit per counter.",
|
||||
"exists" : "true",
|
||||
"poke_mask" : "0x7d",
|
||||
"mask" : "0x7d",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"dcsr" : {
|
||||
"debug" : "true",
|
||||
"exists" : "true",
|
||||
"mask" : "0x00008c04",
|
||||
"poke_mask" : "0x00008dcc",
|
||||
"reset" : "0x40000003"
|
||||
},
|
||||
"time" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mhpmevent5" : {
|
||||
"exists" : "true",
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"pmpaddr8" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpcfg3" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mitbnd1" : {
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0xffffffff",
|
||||
"exists" : "true",
|
||||
"number" : "0x7d6"
|
||||
},
|
||||
"mitcnt0" : {
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff",
|
||||
"number" : "0x7d2",
|
||||
"exists" : "true"
|
||||
},
|
||||
"miccmect" : {
|
||||
"exists" : "true",
|
||||
"number" : "0x7f1",
|
||||
"mask" : "0xffffffff",
|
||||
"reset" : "0x0"
|
||||
},
|
||||
"mhpmcounter6" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"mhpmcounter5h" : {
|
||||
"exists" : "true",
|
||||
"reset" : "0x0",
|
||||
"mask" : "0xffffffff"
|
||||
},
|
||||
"pmpaddr7" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"pmpaddr5" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"mitctl0" : {
|
||||
"number" : "0x7d4",
|
||||
"exists" : "true",
|
||||
"mask" : "0x00000007",
|
||||
"reset" : "0x1"
|
||||
},
|
||||
"meicurpl" : {
|
||||
"exists" : "true",
|
||||
"number" : "0xbcc",
|
||||
"reset" : "0x0",
|
||||
"comment" : "External interrupt current priority level.",
|
||||
"mask" : "0xf"
|
||||
},
|
||||
"pmpaddr10" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"meipt" : {
|
||||
"exists" : "true",
|
||||
"number" : "0xbc9",
|
||||
"reset" : "0x0",
|
||||
"comment" : "External interrupt priority threshold.",
|
||||
"mask" : "0xf"
|
||||
},
|
||||
"pmpaddr15" : {
|
||||
"exists" : "false"
|
||||
},
|
||||
"dicawics" : {
|
||||
"mask" : "0x0130fffc",
|
||||
"reset" : "0x0",
|
||||
"comment" : "Cache diagnostics.",
|
||||
"debug" : "true",
|
||||
"exists" : "true",
|
||||
"number" : "0x7c8"
|
||||
},
|
||||
"mhartid" : {
|
||||
"exists" : "true",
|
||||
"mask" : "0x0",
|
||||
"poke_mask" : "0xfffffff0",
|
||||
"reset" : "0x0"
|
||||
}
|
||||
},
|
||||
"memory_mapped_registers" : {
|
||||
"registers" : {
|
||||
"meigwclr" : {
|
||||
"mask" : "0x0",
|
||||
"address" : "0xf00c5004",
|
||||
"count" : 31
|
||||
},
|
||||
"meigwctrl" : {
|
||||
"mask" : "0x3",
|
||||
"address" : "0xf00c4004",
|
||||
"count" : 31
|
||||
},
|
||||
"meip" : {
|
||||
"mask" : "0x0",
|
||||
"address" : "0xf00c1000",
|
||||
"count" : 1
|
||||
},
|
||||
"meie" : {
|
||||
"count" : 31,
|
||||
"address" : "0xf00c2004",
|
||||
"mask" : "0x1"
|
||||
},
|
||||
"meipl" : {
|
||||
"mask" : "0xf",
|
||||
"address" : "0xf00c0004",
|
||||
"count" : 31
|
||||
},
|
||||
"mpiccfg" : {
|
||||
"count" : 1,
|
||||
"address" : "0xf00c3000",
|
||||
"mask" : "0x1"
|
||||
}
|
||||
},
|
||||
"default_mask" : 0,
|
||||
"address" : "0xf00c0000",
|
||||
"size" : "0x8000"
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue