Fix toplevel in FuseSoC core file
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@ -1,6 +1,6 @@
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CAPI=2:
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name : chipsalliance.org:cores:SweRV_EL2:0
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name : chipsalliance.org:cores:SweRV_EL2:1.2
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filesets:
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rtl:
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@ -63,7 +63,7 @@ targets:
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tools:
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verilator :
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mode : lint-only
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toplevel : swerv_wrapper
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toplevel : el2_swerv_wrapper
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synth:
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default_tool : vivado
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@ -74,7 +74,7 @@ targets:
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vivado:
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part : xc7a100tcsg324-1
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pnr : none
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toplevel : swerv_wrapper
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toplevel : el2_swerv_wrapper
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generate:
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swerv_default_config:
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