Added new files for release 1.1

testbench/asm/cmark_iccm.ld

@@ -0,0 +1,17 @@
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+MEMORY {
+    EXTCODE : ORIGIN = 0,          LENGTH = 0x10000
+    EXTDATA : ORIGIN = 0x10000,    LENGTH = 0x10000
+    ICCM    : ORIGIN = 0xee000000, LENGTH = 0x80000
+    DCCM    : ORIGIN = 0xf0040000, LENGTH = 0x10000
+}
+SECTIONS {
+  .text_init : {*(.text_init)} > EXTCODE
+  init_end = .;
+  .data.ctl : AT(0x1ffec) { LONG(ADDR(.text)); LONG(text_end); LONG(LOADADDR(.text)); LONG(0xf0040000); LONG(STACK)}>EXTDATA
+  .text : AT(init_end)  { *(.text) *(.text.startup)} > ICCM
+   text_end = .;
+  .data  : AT(0x10000)  { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000;} > DCCM
+}

testbench/asm/hello_world_iccm.ld

@@ -0,0 +1,13 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+SECTIONS {
+  .text  :  { *(.text*) }
+  . = 0x10000;
+  .data  :  { *(.*data) *(.rodata*)}
+  . = ALIGN(4);
+  printf_start = .;
+  . = 0xee000000;
+  .data_load : AT(printf_start) {*(.data_text)}
+  printf_end = printf_start + SIZEOF(.data_load);
+}

testbench/asm/hello_world_iccm.s

@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2019 Western Digital Corporation or its affiliates.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+
+// Assembly code for Hello World
+// Not using only ALU ops for creating the string
+
+
+#include "defines.h"
+
+#define STDOUT 0xd0580000
+
+    .set    mfdc, 0x7f9
+.extern printf_start, printf_end
+// Code to execute
+.section .text
+.global _start
+_start:
+
+
+
+    // Enable Caches in MRAC
+    li x1, 0x5f555555
+    csrw 0x7c0, x1
+    li  x3, 4
+    csrw    mfdc, x3        // disable store merging
+    li  x3, RV_ICCM_SADR
+    la  x4, printf_start
+    la  x5, printf_end
+
+
+load:
+    lw  x6, 0 (x4)
+    sw  x6, 0 (x3)
+    addi    x4,x4,4
+    addi    x3,x3,4
+    bltu x4, x5, load
+
+    fence.i
+    call printf
+
+// Write 0xff to STDOUT for TB to termiate test.
+_finish:
+    li x3, STDOUT
+    addi x5, x0, 0xff
+    sb x5, 0(x3)
+    beq x0, x0, _finish
+.rept 100
+    nop
+.endr
+
+.data
+hw_data:
+.ascii "----------------------------------------\n"
+.ascii "Hello World from SweRV EL2 ICCM  @WDC !!\n"
+.ascii "----------------------------------------\n"
+.byte 0
+
+.section .data_text, "ax"
+    // Load string from hw_data
+    // and write to stdout address
+
+printf:
+    li x3, STDOUT
+    la x4, hw_data
+
+loop:
+   lb x5, 0(x4)
+   sb x5, 0(x3)
+   addi x4, x4, 1
+   bnez x5, loop
+   ret
+.long   0,1,2,3,4

testbench/axi_lsu_dma_bridge.sv

@@ -0,0 +1,201 @@
+
+// connects LSI master to external AXI slave and DMA slave
+module axi_lsu_dma_bridge
+#(
+parameter M_ID_WIDTH = 8,
+parameter S0_ID_WIDTH = 8
+)
+(
+input                   clk,
+input                   reset_l,
+
+// master read bus
+input                   m_arvalid,
+input [M_ID_WIDTH-1:0]  m_arid,
+input[31:0]             m_araddr,
+output                  m_arready,
+
+output                  m_rvalid,
+input                   m_rready,
+output [63:0]           m_rdata,
+output [M_ID_WIDTH-1:0] m_rid,
+output [1:0]            m_rresp,
+output                  m_rlast,
+
+// master write bus
+input                   m_awvalid,
+input [M_ID_WIDTH-1:0]  m_awid,
+input[31:0]             m_awaddr,
+output                  m_awready,
+
+input                   m_wvalid,
+output                  m_wready,
+
+output[1:0]             m_bresp,
+output                  m_bvalid,
+output[M_ID_WIDTH-1:0]  m_bid,
+input                   m_bready,
+
+// slave 0 if general ext memory
+output                  s0_arvalid,
+input                   s0_arready,
+
+input                   s0_rvalid,
+input[S0_ID_WIDTH-1:0]  s0_rid,
+input[1:0]              s0_rresp,
+input[63:0]             s0_rdata,
+input                   s0_rlast,
+output                  s0_rready,
+
+output                  s0_awvalid,
+input                   s0_awready,
+
+output                  s0_wvalid,
+input                   s0_wready,
+
+input[1:0]              s0_bresp,
+input                   s0_bvalid,
+input[S0_ID_WIDTH-1:0]  s0_bid,
+output                  s0_bready,
+
+// slave 1 if DMA port
+output                  s1_arvalid,
+input                   s1_arready,
+
+input                   s1_rvalid,
+input[1:0]              s1_rresp,
+input[63:0]             s1_rdata,
+input                   s1_rlast,
+output                  s1_rready,
+
+output                  s1_awvalid,
+input                   s1_awready,
+
+output                  s1_wvalid,
+input                   s1_wready,
+
+input[1:0]              s1_bresp,
+input                   s1_bvalid,
+output                  s1_bready
+);
+
+parameter ICCM_BASE = `RV_ICCM_BITS; // in LSBs
+localparam IDFIFOSZ = $clog2(`RV_DMA_BUF_DEPTH);
+bit[31:0] iccm_real_base_addr = `RV_ICCM_SADR ;
+
+wire ar_slave_select;
+wire aw_slave_select;
+wire w_slave_select;
+
+wire rresp_select;
+wire bresp_select;
+wire ar_iccm_select;
+wire aw_iccm_select;
+
+reg [1:0] wsel_iptr, wsel_optr;
+reg [2:0] wsel_count;
+reg [3:0] wsel;
+
+
+reg [M_ID_WIDTH-1:0] arid [1<<IDFIFOSZ];
+reg [M_ID_WIDTH-1:0] awid [1<<IDFIFOSZ];
+reg [IDFIFOSZ-1:0] arid_cnt;
+reg [IDFIFOSZ-1:0] awid_cnt;
+reg [IDFIFOSZ-1:0] rid_cnt;
+reg [IDFIFOSZ-1:0] bid_cnt;
+
+
+// 1 select slave 1; 0 - slave 0
+assign ar_slave_select = ar_iccm_select;
+assign aw_slave_select = aw_iccm_select;
+
+assign ar_iccm_select = m_araddr[31:ICCM_BASE] == iccm_real_base_addr[31:ICCM_BASE];
+assign aw_iccm_select = m_awaddr[31:ICCM_BASE] == iccm_real_base_addr[31:ICCM_BASE];
+
+assign s0_arvalid = m_arvalid & ~ar_slave_select;
+assign s1_arvalid = m_arvalid &  ar_slave_select;
+assign m_arready = ar_slave_select ? s1_arready : s0_arready;
+
+
+assign s0_awvalid = m_awvalid & ~aw_slave_select;
+assign s1_awvalid = m_awvalid & aw_slave_select;
+assign m_awready = aw_slave_select ? s1_awready : s0_awready;
+
+
+assign s0_wvalid = m_wvalid & ~w_slave_select;
+assign s1_wvalid = m_wvalid &  w_slave_select;
+assign m_wready = w_slave_select ? s1_wready : s0_wready;
+assign w_slave_select = (wsel_count == 0 || wsel_count[2]) ? aw_slave_select : wsel[wsel_optr];
+
+assign m_rvalid = s0_rvalid | s1_rvalid;
+assign s0_rready = m_rready & ~rresp_select;
+assign s1_rready = m_rready &  rresp_select;
+assign m_rdata = rresp_select ? s1_rdata : s0_rdata;
+assign m_rresp = rresp_select ? s1_rresp : s0_rresp;
+assign m_rid = rresp_select ? arid[rid_cnt] : s0_rid;
+assign m_rlast = rresp_select ? s1_rlast : s0_rlast;
+
+assign rresp_select = s1_rvalid & ~s0_rvalid;
+
+assign m_bvalid = s0_bvalid | s1_bvalid;
+assign s0_bready = m_bready & ~bresp_select;
+assign s1_bready = m_bready &  bresp_select;
+assign m_bid = bresp_select ? awid[bid_cnt] : s0_bid;
+assign m_bresp = bresp_select ? s1_bresp : s0_bresp;
+
+
+assign bresp_select = s1_bvalid & ~s0_bvalid;
+
+
+// W-channel select fifo
+always @ (posedge clk or negedge reset_l)
+    if(!reset_l) begin
+        wsel_count <= '0;
+        wsel_iptr <= '0;
+        wsel_optr <= '0;
+    end
+    else begin
+        if(m_awvalid & m_awready) begin
+            wsel[wsel_iptr] <= aw_slave_select;
+            if(!(m_wready & m_wvalid )) wsel_count <= wsel_count + 1;
+            wsel_iptr <= wsel_iptr + 1;
+        end
+        if(m_wvalid & m_wready) begin
+           if(!(m_awready & m_awvalid ) ) wsel_count <= wsel_count - 1;
+           wsel_optr <= wsel_optr + 1;
+        end
+    end
+
+// id replacement for narrow ID slave
+always @ (posedge clk or negedge reset_l)
+    if(!reset_l) begin
+        arid_cnt <= '0;
+        rid_cnt <= '0;
+    end
+    else begin
+        if(ar_slave_select & m_arready & m_arvalid) begin
+            arid[arid_cnt] <= m_arid;
+            arid_cnt <= arid_cnt + 1;
+        end
+        if(rresp_select & m_rready & m_rvalid) begin
+            rid_cnt <= rid_cnt + 1;
+        end
+
+    end
+
+always @ (posedge clk or negedge reset_l)
+    if(!reset_l) begin
+        awid_cnt <= '0;
+        bid_cnt <= '0;
+    end
+    else begin
+        if(aw_slave_select & m_awready & m_awvalid) begin
+            awid[awid_cnt] <= m_awid;
+            awid_cnt <= awid_cnt + 1;
+        end
+        if(bresp_select & m_bready & m_bvalid) begin
+            bid_cnt <= bid_cnt + 1;
+        end
+    end
+
+endmodule