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cores-swerv-el2
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Enable gdb by openocd.

This commit is contained in:
colin 2022-03-08 09:18:19 +00:00
parent ddf80fde8d
commit d86fef92e2
6 changed files with 35 additions and 17 deletions
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6
demo/jtag/Makefile
View File

@ -16,6 +16,7 @@ ifdef debug
endif
LINK = $(DEMODIR)/link.ld
LINKPRO = $(DEMODIR)/link_pro.ld
# CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
CFLAGS += "-std=c++11"
@ -61,8 +62,9 @@ sim:
program.hex: $(TEST).o $(LINK)
@echo Building $(TEST)
$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINK) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(TEST).o -nostartfiles $(TEST_LIBS)
$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINKPRO) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(TEST).o -nostartfiles $(TEST_LIBS)
$(GCC_PREFIX)-objcopy -O verilog $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/program.hex
$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINK) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(TEST).o -nostartfiles $(TEST_LIBS)
$(GCC_PREFIX)-objdump -S $(BUILD_DIR)/$(TEST).bin > $(BUILD_DIR)/$(TEST).dis
@echo Completed building $(TEST)
@ -76,7 +78,7 @@ openocd:
openocd -f swerv.cfg
gdb:
$(GDB_PREFIX) -x gdbinit
$(GDB_PREFIX) -x gdbinit ./build/jtag.bin
help:
@echo Possible targets: verilator help clean all verilator-build program.hex

4
demo/jtag/gdbinit
View File

@ -1,3 +1,3 @@
set debug remote 1
# set debug remote 1
target extended-remote :3333
set remotetimeout 5000
set remotetimeout 2000

4
demo/jtag/link.ld
View File

@ -4,11 +4,11 @@ ENTRY(_start)
SECTIONS
{
. = 0;
. = 0x80000000;
.text_init : { *(.text_init*) }
.text : { *(.text*) }
_end = .;
. = 0x4000;
. = 0x80004000;
.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; }
.bss : { *(.bss) }
. = 0xd0580000;

16
demo/jtag/link_pro.ld Normal file
View File

@ -0,0 +1,16 @@
OUTPUT_ARCH( "riscv" )
ENTRY(_start)
SECTIONS
{
. = 0x0000;
.text_init : { *(.text_init*) }
.text : { *(.text*) }
_end = .;
. = 0x4000;
.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x2000; }
.bss : { *(.bss) }
. = 0xd0580000;
.data.io : { *(.data.io) }
}

2
soc/ahb_sif.sv
View File

@ -53,7 +53,7 @@ module axi_slv #(
output reg [TAGW-1:0] bid
);
parameter MEM_DEPTH = 17; // memory size = 0x8000 = 32k
parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k
bit [7:0] mem[(1<<MEM_DEPTH)-1:0];

20
soc/swerv.config
View File

@ -267,23 +267,23 @@ my $text_in_iccm = 0;
my $lsu2dma = 0;
$ret_stack_size=8;
$ret_stack_size=4;
$btb_enable=1;
$btb_fullya=0;
$btb_toffset_size=12;
$btb_size=512;
$bht_size=512;
$btb_size=32;
$bht_size=128;
$dccm_enable=1;
$dccm_region="0xf";
$dccm_offset="0x40000"; #1*256*1024
$dccm_size=64;
$dccm_num_banks=4;
$iccm_enable=1;
$dccm_size=32;
$dccm_num_banks=8;
$iccm_enable=0;
$iccm_region="0xe";
$top_align_iccm = 1;
$iccm_offset="0xe000000"; #0x380*256*1024
$iccm_size=64;
$iccm_num_banks=4;
$iccm_size=32;
$iccm_num_banks=8;
$icache_enable=1;
$icache_waypack=1;
$icache_num_ways=2;
@ -291,13 +291,13 @@ $icache_banks_way=2;
$icache_2banks=1;
$icache_bank_width=8;
$icache_ln_sz=64;
$icache_ecc=1;
$icache_ecc=0;
$icache_size=16;
$pic_2cycle=0;
$pic_region="0xf";
$pic_offset="0xc0000"; # 3*256*1024
$pic_size=32;
$pic_total_int=31;
$pic_total_int=8;
$load_to_use_plus1=0;
$lsu_stbuf_depth=4;
$dma_buf_depth=5;