diff --git a/demo/jtag/synth.sh b/demo/jtag/synth.sh
index 0434120..cc68e09 100755
--- a/demo/jtag/synth.sh
+++ b/demo/jtag/synth.sh
@@ -19,12 +19,11 @@ RTL=$(cat ../../soc/soc_top.mk)
 
 rtl_files=""
 
-
+rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_pdef.vh "
+rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/common_defines.vh "
 rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pd_defines.vh "
-# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/common_defines.vh "
-# # rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pic_map_auto.h "
-# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_pdef.vh "
 # rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_param.vh "
+# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pic_map_auto.h "
 
 for src in $RTL; do
 	rtl_files="$rtl_files $SOC/$src"
@@ -39,6 +38,7 @@ filelist=""
 for file in $rtl_files; do
 	filelist="$filelist $file"
 done
+# sv2v $filelist > gen/soc_top.v
 sv2v -Ibuild $filelist > gen/soc_top.v
 
 {
diff --git a/soc/soc_sim.sv b/soc/soc_sim.sv
index dd65d55..750bf89 100644
--- a/soc/soc_sim.sv
+++ b/soc/soc_sim.sv
@@ -170,6 +170,8 @@ module soc_sim (
     fd = $fopen("console.log", "w");
     commit_count = 0;
 
+    $readmemh("program.hex", rvsoc.lmem.mem);
+    $readmemh("program.hex", rvsoc.imem.mem);
   end
 
   assign rst_l = cycleCnt > 20;
diff --git a/soc/soc_top.sv b/soc/soc_top.sv
index 8045e04..d9eb66e 100644
--- a/soc/soc_top.sv
+++ b/soc/soc_top.sv
@@ -296,9 +296,6 @@ module soc_top (
     nmi_vector = 32'hee000000;
     nmi_int = 0;
 
-    $readmemh("program.hex", lmem.mem);
-    $readmemh("program.hex", imem.mem);
-
   end
 
   el2_swerv_wrapper rvtop (