Add Verilator gen dot graph.

demo/Makefile

@@ -50,6 +50,24 @@ verilator-build: swerv_define
 	cp ${DEMODIR}/test_soc_sim.cpp obj_dir
 	$(MAKE) -j -e -C obj_dir/ -f Vsoc_sim.mk $(VERILATOR_MAKE_FLAGS)
 
+verilator-build-xml: swerv_define
+	echo '`undef RV_ASSERT_ON' >> ${BUILD_DIR}/common_defines.vh
+	verilator --xml-only -CFLAGS ${CFLAGS} \
+	              $(BUILD_DIR)/common_defines.vh \
+								$(BUILD_DIR)/el2_pdef.vh \
+	              -I${BUILD_DIR} \
+								-Wno-WIDTH \
+	              -Wno-UNOPTFLAT \
+	              -F ${RV_SOC}/soc_top.mk \
+	              -F ${RV_SOC}/soc_sim.mk \
+	              $(RV_SOC)/soc_sim.sv \
+	              --top-module soc_sim -exe test_soc_sim.cpp --autoflush $(VERILATOR_DEBUG) \
+								-o graph.dot
+	cp ${DEMODIR}/test_soc_sim.cpp obj_dir
+	cp ${DEMODIR}/gendot.py obj_dir
+	python3 gendot.py
+	dot -Tpdf -o ./obj_dir/graph.pdf ./obj_dir/graph.dot
+
 ##################### Simulation Runs #####################################
 
 verilator: program.hex verilator-build

demo/gendot.py

@@ -0,0 +1,68 @@
+#!/usr/bin/env python3
+# -*- Python -*- See copyright, etc below
+# pylint: disable=C0103,C0114,C0115,C0115,C0116,R0914
+######################################################################
+
+import argparse
+import os
+import subprocess
+import tempfile
+import xml.etree.ElementTree as ET
+# from pprint import pprint, pformat
+
+#######################################################################
+
+
+class VlHierGraph:
+    def __init__(self, output_filename='./obj_dir/graph.dot'):  # output filename
+
+        self.name_to_number = {}
+        xml_temp = "./obj_dir/Vsoc_sim.xml"
+        self.next_vertex_number = 0
+        self.tree = ET.parse(xml_temp)
+
+        with open(output_filename, "w") as fh:
+            # For more serious purposes, use the python graphviz package instead
+            fh.write("digraph {\n")
+            fh.write("  dpi=300;\n")
+            fh.write("  order=LR;\n")
+            fh.write(
+                "  node [fontsize=8 shape=\"box\" margin=0.01 width=0 height=0]"
+            )
+            fh.write("  edge [fontsize=6]")
+            # Find cells
+            root = self.tree.getroot()
+            netlist = root.find('netlist')
+            for module in netlist.findall('module'):
+                # origNames are before parameterization, name if after
+                mod_name = module.get('name')
+                mod_number = self.name_to_vertex_number(mod_name)
+                fh.write("  n%d [label=\"%s\"" % (mod_number, mod_name))
+                if module.get('topModule'):
+                    fh.write(" color=\"red\" rank=1")
+                fh.write("];\n")
+
+                for instance in module.findall('instance'):
+                    inst_name = instance.get('name')
+                    def_name = instance.get('defName')
+                    def_number = self.name_to_vertex_number(def_name)
+                    fh.write("  n%d->n%d [label=\"%s\"];\n" %
+                             (mod_number, def_number, inst_name))
+
+            fh.write("}\n")
+
+    def name_to_vertex_number(self, name):
+        if name not in self.name_to_number:
+            self.next_vertex_number += 1
+            self.name_to_number[name] = self.next_vertex_number
+        return self.name_to_number[name]
+
+
+#######################################################################
+if __name__ == '__main__':
+    fc = VlHierGraph()
+
+######################################################################
+# Local Variables:
+# compile-command: "./vl_hier_graph -h ; VERILATOR_ROOT=$V4 ./vl_hier_graph +define+thru top.v"
+# End: