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Branch 1.4

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Joseph Rahmeh 2021-04-19 07:56:12 -07:00
parent 9260b5567c
commit fb3354352b
32 changed files with 3237 additions and 5228 deletions
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11
README.md
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@ -1,6 +1,6 @@
# EL2 SweRV RISC-V Core<sup>TM</sup> 1.3 from Western Digital # EL2 SweRV RISC-V Core<sup>TM</sup> 1.3 from Western Digital
This repository contains the SweRV EL2 Core<sup>TM</sup> design RTL This repository contains the EL2 RISC-V SweRV Core<sup>TM</sup> design RTL
## License ## License
@ -53,7 +53,7 @@ For example to build with a DCCM of size 64 Kb:
`% $RV_ROOT/configs/swerv.config -dccm_size=64` `% $RV_ROOT/configs/swerv.config -dccm_size=64`
This will update the **default** snapshot in $RV_ROOT/configs/snapshots/default/ with parameters for a 64K DCCM. This will update the **default** snapshot in ./snapshots/default/ with parameters for a 64K DCCM.
Add `-snapshot=dccm64`, for example, if you wish to name your build snapshot *dccm64* and refer to it during the build. Add `-snapshot=dccm64`, for example, if you wish to name your build snapshot *dccm64* and refer to it during the build.
@ -70,7 +70,7 @@ target``typical_pd``.**
This script derives the following consistent set of include files : This script derives the following consistent set of include files :
$RV_ROOT/configs/snapshots/default ./snapshots/default
├── common_defines.vh # `defines for testbench or design ├── common_defines.vh # `defines for testbench or design
├── defines.h # #defines for C/assembly headers ├── defines.h # #defines for C/assembly headers
├── el2_param.vh # Design parameters ├── el2_param.vh # Design parameters
@ -99,13 +99,10 @@ Example for csh or its derivatives:
*(Name your snapshot to distinguish it from the default. Without an explicit name, it will update/override the __default__ snapshot)* *(Name your snapshot to distinguish it from the default. Without an explicit name, it will update/override the __default__ snapshot)*
For example if `mybuild` is the name for the snapshot: For example if `mybuild` is the name for the snapshot:
set BUILD_PATH environment variable:
`setenv BUILD_PATH snapshots/mybuild`
`$RV_ROOT/configs/swerv.config [configuration options..] -snapshot=mybuild` `$RV_ROOT/configs/swerv.config [configuration options..] -snapshot=mybuild`
Snapshots are placed in `$BUILD_PATH` directory Snapshots are placed in ./snapshots directory
1. Running a simple Hello World program (verilator) 1. Running a simple Hello World program (verilator)

17
configs/swerv.config
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@ -37,7 +37,7 @@ my @verilog_vars = qw (xlen config_key reset_vec tec_rv_icg numiregs nmi_vec tar
# Include these macros in assembly (pattern matched) # Include these macros in assembly (pattern matched)
my @asm_vars = qw (xlen reset_vec nmi_vec target dccm.* iccm.* pic.* memmap testbench.* protection.* core.*); my @asm_vars = qw (xlen reset_vec nmi_vec target dccm.* iccm.* pic.* memmap testbench.* protection.* core.*);
my @asm_overridable = qw (reset_vec nmi_vec) ; my @asm_overridable = qw (reset_vec nmi_vec serialio external_data) ;
# Include these macros in PD (pattern matched) # Include these macros in PD (pattern matched)
my @pd_vars = qw (physical retstack target btb.* bht.* dccm.* iccm.* icache.* pic.* bus.* reset_vec nmi_vec build_ahb_lite datawidth ); my @pd_vars = qw (physical retstack target btb.* bht.* dccm.* iccm.* icache.* pic.* bus.* reset_vec nmi_vec build_ahb_lite datawidth );
@ -308,9 +308,9 @@ my $div_new=1; # old or new div algorithm
my $fpga_optimize = 1; my $fpga_optimize = 1;
# Default bitmanip options # Default bitmanip options
my $bitmanip_zba = 0; my $bitmanip_zba = 1;
my $bitmanip_zbb = 1; my $bitmanip_zbb = 1;
my $bitmanip_zbc = 0; my $bitmanip_zbc = 1;
my $bitmanip_zbe = 0; my $bitmanip_zbe = 0;
my $bitmanip_zbf = 0; my $bitmanip_zbf = 0;
my $bitmanip_zbp = 0; my $bitmanip_zbp = 0;
@ -504,7 +504,7 @@ our %csr = (#{{{
"exists" => "true", "exists" => "true",
}, },
"mimpid" => { "mimpid" => {
"reset" => "0x3", "reset" => "0x4",
"mask" => "0x0", "mask" => "0x0",
"exists" => "true", "exists" => "true",
}, },
@ -904,7 +904,7 @@ our %config = (#{{{
"bitmanip_zbs" => $bitmanip_zbs, # Design Parm, Overridable "bitmanip_zbs" => $bitmanip_zbs, # Design Parm, Overridable
"fast_interrupt_redirect" => "$fast_interrupt_redirect", # Design Parm, Overridable "fast_interrupt_redirect" => "$fast_interrupt_redirect", # Design Parm, Overridable
"lsu2dma" => $lsu2dma, # used by design/TB for LSU to DMA bridge "lsu2dma" => $lsu2dma, # used by design/TB for LSU to DMA bridge
"fpga_optimize" => $fpga_optimize # Optimize fpga speed by removing clock gating "fpga_optimize" => $fpga_optimize # Design Parm, Overridable
}, },
"dccm" => { "dccm" => {
@ -1986,7 +1986,6 @@ my $pddata='
`include "common_defines.vh" `include "common_defines.vh"
`undef RV_ASSERT_ON `undef RV_ASSERT_ON
`undef TEC_RV_ICG `undef TEC_RV_ICG
`define TEC_RV_ICG HDBLVT16_CKGTPLT_V5_12
`define RV_PHYSICAL 1 `define RV_PHYSICAL 1
'; ';
@ -2595,8 +2594,10 @@ SECTIONS
. = $io; . = $io;
.data.io . : { *(.data.io) } .data.io . : { *(.data.io) }
$data_loc $data_loc
.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; } .data : ALIGN(0x800) { *(.*data) *(.rodata*)}
.bss : { *(.bss) } .bss : {BSS_START = .; *(.*bss)}
BSS_END = .;
STACK = ALIGN(16) + 0x1000;
$iccm_ctl $iccm_ctl
$dccm_ctl $dccm_ctl
} }

7
design/dbg/el2_dbg.sv
View File

@ -108,6 +108,7 @@ import el2_pkg::*;
// general inputs // general inputs
input logic clk, input logic clk,
input logic free_clk,
input logic rst_l, // This includes both top rst and debug rst input logic rst_l, // This includes both top rst and debug rst
input logic dbg_rst_l, input logic dbg_rst_l,
input logic clk_override, input logic clk_override,
@ -247,6 +248,7 @@ import el2_pkg::*;
logic [2:0] sb_axi_size; logic [2:0] sb_axi_size;
logic dbg_dm_rst_l; logic dbg_dm_rst_l;
logic rst_l_sync;
//clken //clken
logic dbg_free_clken; logic dbg_free_clken;
@ -271,6 +273,9 @@ import el2_pkg::*;
assign dbg_dm_rst_l = dbg_rst_l & (dmcontrol_reg[0] | scan_mode); assign dbg_dm_rst_l = dbg_rst_l & (dmcontrol_reg[0] | scan_mode);
assign dbg_core_rst_l = ~dmcontrol_reg[1] | scan_mode; assign dbg_core_rst_l = ~dmcontrol_reg[1] | scan_mode;
// synchronize the rst
rvsyncss #(1) rstl_syncff (.din(rst_l), .dout(rst_l_sync), .clk(free_clk), .rst_l(dbg_rst_l));
// system bus register // system bus register
// sbcs[31:29], sbcs - [22]:sbbusyerror, [21]: sbbusy, [20]:sbreadonaddr, [19:17]:sbaccess, [16]:sbautoincrement, [15]:sbreadondata, [14:12]:sberror, sbsize=32, 128=0, 64/32/16/8 are legal // sbcs[31:29], sbcs - [22]:sbbusyerror, [21]: sbbusy, [20]:sbreadonaddr, [19:17]:sbaccess, [16]:sbautoincrement, [15]:sbreadondata, [14:12]:sberror, sbsize=32, 128=0, 64/32/16/8 are legal
assign sbcs_reg[31:29] = 3'b1; assign sbcs_reg[31:29] = 3'b1;
@ -362,7 +367,7 @@ import el2_pkg::*;
assign dmstatus_haveresetn_wren = (dmi_reg_addr == 7'h10) & dmi_reg_wdata[28] & dmi_reg_en & dmi_reg_wr_en & dmcontrol_reg[0]; // clear the havereset assign dmstatus_haveresetn_wren = (dmi_reg_addr == 7'h10) & dmi_reg_wdata[28] & dmi_reg_en & dmi_reg_wr_en & dmcontrol_reg[0]; // clear the havereset
assign dmstatus_havereset = ~dmstatus_haveresetn; assign dmstatus_havereset = ~dmstatus_haveresetn;
assign dmstatus_unavail = dmcontrol_reg[1] | ~rst_l; assign dmstatus_unavail = dmcontrol_reg[1] | ~rst_l_sync;
assign dmstatus_running = ~(dmstatus_unavail | dmstatus_halted); assign dmstatus_running = ~(dmstatus_unavail | dmstatus_halted);
rvdffs #(1) dmstatus_resumeack_reg (.din(dmstatus_resumeack_din), .dout(dmstatus_resumeack), .en(dmstatus_resumeack_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk)); rvdffs #(1) dmstatus_resumeack_reg (.din(dmstatus_resumeack_din), .dout(dmstatus_resumeack), .en(dmstatus_resumeack_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));

2
design/dec/csrdecode
View File

@ -214,7 +214,7 @@ csr[ csr_mfdc ] = { csr_mfdc presync postsync }
csr[ csr_dcsr ] = { csr_dcsr } csr[ csr_dcsr ] = { csr_dcsr }
csr[ csr_dpc ] = { csr_dpc } csr[ csr_dpc ] = { csr_dpc }
csr[ csr_mtsel ] = { csr_mtsel } csr[ csr_mtsel ] = { csr_mtsel }
csr[ csr_mtdata1 ] = { csr_mtdata1 postsync } csr[ csr_mtdata1 ] = { csr_mtdata1 presync postsync }
csr[ csr_mtdata2 ] = { csr_mtdata2 postsync } csr[ csr_mtdata2 ] = { csr_mtdata2 postsync }
csr[ csr_mhpmc3 ] = { csr_mhpmc3 presync } csr[ csr_mhpmc3 ] = { csr_mhpmc3 presync }
csr[ csr_mhpmc4 ] = { csr_mhpmc4 presync } csr[ csr_mhpmc4 ] = { csr_mhpmc4 presync }

143
design/dec/decode
View File

@ -3,23 +3,53 @@
clz = [011000000000.....001.....0010011] clz = [011000000000.....001.....0010011]
ctz = [011000000001.....001.....0010011] ctz = [011000000001.....001.....0010011]
pcnt = [011000000010.....001.....0010011] cpop = [011000000010.....001.....0010011]
sext_b = [011000000100.....001.....0010011] sext_b = [011000000100.....001.....0010011]
sext_h = [011000000101.....001.....0010011] sext_h = [011000000101.....001.....0010011]
slo = [0010000..........001.....0110011]
sro = [0010000..........101.....0110011]
sloi = [0010000..........001.....0010011]
sroi = [0010000..........101.....0010011]
min = [0000101..........100.....0110011] min = [0000101..........100.....0110011]
max = [0000101..........101.....0110011] max = [0000101..........110.....0110011]
minu = [0000101..........110.....0110011] minu = [0000101..........101.....0110011]
maxu = [0000101..........111.....0110011] maxu = [0000101..........111.....0110011]
andn = [0100000..........111.....0110011] andn = [0100000..........111.....0110011]
orn = [0100000..........110.....0110011] orn = [0100000..........110.....0110011]
xnor = [0100000..........100.....0110011] xnor = [0100000..........100.....0110011]
pack = [0000100..........100.....0110011]
#pack = [0000100..........100.....0110011]
zext_h = [000010000000.....100.....0110011]
pack1 = [000010000001.....100.....0110011]
pack2 = [000010000010.....100.....0110011]
pack3 = [000010000011.....100.....0110011]
pack4 = [000010000100.....100.....0110011]
pack5 = [000010000101.....100.....0110011]
pack6 = [000010000110.....100.....0110011]
pack7 = [000010000111.....100.....0110011]
pack8 = [000010001000.....100.....0110011]
pack9 = [000010001001.....100.....0110011]
pack10 = [000010001010.....100.....0110011]
pack11 = [000010001011.....100.....0110011]
pack12 = [000010001100.....100.....0110011]
pack13 = [000010001101.....100.....0110011]
pack14 = [000010001110.....100.....0110011]
pack15 = [000010001111.....100.....0110011]
pack16 = [000010010000.....100.....0110011]
pack17 = [000010010001.....100.....0110011]
pack18 = [000010010010.....100.....0110011]
pack19 = [000010010011.....100.....0110011]
pack20 = [000010010100.....100.....0110011]
pack21 = [000010010101.....100.....0110011]
pack22 = [000010010110.....100.....0110011]
pack23 = [000010010111.....100.....0110011]
pack24 = [000010011000.....100.....0110011]
pack25 = [000010011001.....100.....0110011]
pack26 = [000010011010.....100.....0110011]
pack27 = [000010011011.....100.....0110011]
pack28 = [000010011100.....100.....0110011]
pack29 = [000010011101.....100.....0110011]
pack30 = [000010011110.....100.....0110011]
pack31 = [000010011111.....100.....0110011]
packu = [0100100..........100.....0110011] packu = [0100100..........100.....0110011]
packh = [0000100..........111.....0110011] packh = [0000100..........111.....0110011]
rol = [0110000..........001.....0110011] rol = [0110000..........001.....0110011]
@ -30,15 +60,15 @@ sh1add = [0010000..........010.....0110011]
sh2add = [0010000..........100.....0110011] sh2add = [0010000..........100.....0110011]
sh3add = [0010000..........110.....0110011] sh3add = [0010000..........110.....0110011]
sbset = [0010100..........001.....0110011] bset = [0010100..........001.....0110011]
sbclr = [0100100..........001.....0110011] bclr = [0100100..........001.....0110011]
sbinv = [0110100..........001.....0110011] binv = [0110100..........001.....0110011]
sbext = [0100100..........101.....0110011] bext = [0100100..........101.....0110011]
sbseti = [0010100..........001.....0010011] bseti = [0010100..........001.....0010011]
sbclri = [0100100..........001.....0010011] bclri = [0100100..........001.....0010011]
sbinvi = [0110100..........001.....0010011] binvi = [0110100..........001.....0010011]
sbexti = [0100100..........101.....0010011] bexti = [0100100..........101.....0010011]
grev = [0110100..........101.....0110011] grev = [0110100..........101.....0110011]
#grevi = [01101............101.....0010011] #grevi = [01101............101.....0010011]
@ -74,8 +104,7 @@ grevi27 = [011010011011.....101.....0010011]
grevi28 = [011010011100.....101.....0010011] grevi28 = [011010011100.....101.....0010011]
grevi29 = [011010011101.....101.....0010011] grevi29 = [011010011101.....101.....0010011]
grevi30 = [011010011110.....101.....0010011] grevi30 = [011010011110.....101.....0010011]
#grevi31 = [011010011111.....101.....0010011] # REV grevi31 = [011010011111.....101.....0010011]
rev = [011010011111.....101.....0010011]
gorc = [0010100..........101.....0110011] gorc = [0010100..........101.....0110011]
#gorci = [00101............101.....0010011] #gorci = [00101............101.....0010011]
@ -96,8 +125,7 @@ gorci12 = [001010001100.....101.....0010011]
gorci13 = [001010001101.....101.....0010011] gorci13 = [001010001101.....101.....0010011]
gorci14 = [001010001110.....101.....0010011] gorci14 = [001010001110.....101.....0010011]
gorci15 = [001010001111.....101.....0010011] gorci15 = [001010001111.....101.....0010011]
#gorci16 = [001010010000.....101.....0010011] # ORC16 gorci16 = [001010010000.....101.....0010011]
orc16 = [001010010000.....101.....0010011]
gorci17 = [001010010001.....101.....0010011] gorci17 = [001010010001.....101.....0010011]
gorci18 = [001010010010.....101.....0010011] gorci18 = [001010010010.....101.....0010011]
gorci19 = [001010010011.....101.....0010011] gorci19 = [001010010011.....101.....0010011]
@ -121,8 +149,8 @@ shfli = [00001000.........001.....0010011]
unshfl = [0000100..........101.....0110011] unshfl = [0000100..........101.....0110011]
unshfli = [00001000.........101.....0010011] unshfli = [00001000.........101.....0010011]
bdep = [0100100..........110.....0110011] bdecompress = [0100100..........110.....0110011]
bext = [0000100..........110.....0110011] bcompress = [0000100..........110.....0110011]
clmul = [0000101..........001.....0110011] clmul = [0000101..........001.....0110011]
clmulr = [0000101..........010.....0110011] clmulr = [0000101..........010.....0110011]
@ -137,6 +165,11 @@ crc32c_w = [011000011010.....001.....0010011]
bfp = [0100100..........111.....0110011] bfp = [0100100..........111.....0110011]
xperm_n = [0010100..........010.....0110011]
xperm_b = [0010100..........100.....0110011]
xperm_h = [0010100..........110.....0110011]
@ -348,11 +381,9 @@ rv32i = {
fence_i fence_i
clz clz
ctz ctz
pcnt cpop
sext_b sext_b
sext_h sext_h
slo
sro
min min
max max
pack pack
@ -361,13 +392,13 @@ rv32i = {
rol rol
ror ror
zbb zbb
sbset bset
sbclr bclr
sbinv binv
sbext
zbs
bext bext
bdep zbs
bcompress
bdecompress
zbe zbe
clmul clmul
clmulh clmulh
@ -377,6 +408,9 @@ rv32i = {
gorc gorc
shfl shfl
unshfl unshfl
xperm_n
xperm_b
xperm_h
zbp zbp
crc32_b crc32_b
crc32_h crc32_h
@ -398,13 +432,9 @@ rv32i = {
rv32i[clz] = { alu zbb rs1 rd clz } rv32i[clz] = { alu zbb rs1 rd clz }
rv32i[ctz] = { alu zbb rs1 rd ctz } rv32i[ctz] = { alu zbb rs1 rd ctz }
rv32i[pcnt] = { alu zbb rs1 rd pcnt } rv32i[cpop] = { alu zbb rs1 rd cpop }
rv32i[sext_b] = { alu zbb rs1 rd sext_b} rv32i[sext_b] = { alu zbb rs1 rd sext_b}
rv32i[sext_h] = { alu zbb rs1 rd sext_h} rv32i[sext_h] = { alu zbb rs1 rd sext_h}
rv32i[slo] = { alu zbp rs1 rs2 rd slo }
rv32i[sro] = { alu zbp rs1 rs2 rd sro }
rv32i[sloi] = { alu zbp rs1 rd shimm5 slo }
rv32i[sroi] = { alu zbp rs1 rd shimm5 sro }
rv32i[min] = { alu zbb rs1 rs2 rd sub min } rv32i[min] = { alu zbb rs1 rs2 rd sub min }
rv32i[max] = { alu zbb rs1 rs2 rd sub max } rv32i[max] = { alu zbb rs1 rs2 rd sub max }
rv32i[minu] = { alu zbb rs1 rs2 rd unsign sub min } rv32i[minu] = { alu zbb rs1 rs2 rd unsign sub min }
@ -412,30 +442,33 @@ rv32i[maxu] = { alu zbb rs1 rs2 rd unsign sub max }
rv32i[andn] = { alu zbb zbp rs1 rs2 rd land } rv32i[andn] = { alu zbb zbp rs1 rs2 rd land }
rv32i[orn] = { alu zbb zbp rs1 rs2 rd lor } rv32i[orn] = { alu zbb zbp rs1 rs2 rd lor }
rv32i[xnor] = { alu zbb zbp rs1 rs2 rd lxor } rv32i[xnor] = { alu zbb zbp rs1 rs2 rd lxor }
rv32i[pack] = { alu zbb zbp rs1 rs2 rd pack } rv32i[packu] = { alu zbp rs1 rs2 rd packu }
rv32i[packu] = { alu zbb zbp rs1 rs2 rd packu } rv32i[packh] = { alu zbp rs1 rs2 rd packh zbe zbf}
rv32i[packh] = { alu zbb zbp rs1 rs2 rd packh }
rv32i[rol] = { alu zbb zbp rs1 rs2 rd rol } rv32i[rol] = { alu zbb zbp rs1 rs2 rd rol }
rv32i[ror] = { alu zbb zbp rs1 rs2 rd ror } rv32i[ror] = { alu zbb zbp rs1 rs2 rd ror }
rv32i[rori] = { alu zbb zbp rs1 rd shimm5 ror } rv32i[rori] = { alu zbb zbp rs1 rd shimm5 ror }
rv32i[sbset] = { alu zbs rs1 rs2 rd sbset } rv32i[bset] = { alu zbs rs1 rs2 rd bset }
rv32i[sbclr] = { alu zbs rs1 rs2 rd sbclr } rv32i[bclr] = { alu zbs rs1 rs2 rd bclr }
rv32i[sbinv] = { alu zbs rs1 rs2 rd sbinv } rv32i[binv] = { alu zbs rs1 rs2 rd binv }
rv32i[sbext] = { alu zbs rs1 rs2 rd sbext } rv32i[bext] = { alu zbs rs1 rs2 rd bext }
rv32i[sbseti] = { alu zbs rs1 rd shimm5 sbset } rv32i[bseti] = { alu zbs rs1 rd shimm5 bset }
rv32i[sbclri] = { alu zbs rs1 rd shimm5 sbclr } rv32i[bclri] = { alu zbs rs1 rd shimm5 bclr }
rv32i[sbinvi] = { alu zbs rs1 rd shimm5 sbinv } rv32i[binvi] = { alu zbs rs1 rd shimm5 binv }
rv32i[sbexti] = { alu zbs rs1 rd shimm5 sbext } rv32i[bexti] = { alu zbs rs1 rd shimm5 bext }
rv32i[sh1add] = { alu zba rs1 rs2 rd sh1add} rv32i[sh1add] = { alu zba rs1 rs2 rd sh1add}
rv32i[sh2add] = { alu zba rs1 rs2 rd sh2add} rv32i[sh2add] = { alu zba rs1 rs2 rd sh2add}
rv32i[sh3add] = { alu zba rs1 rs2 rd sh3add} rv32i[sh3add] = { alu zba rs1 rs2 rd sh3add}
#v32i[pack] = { alu zbp rs1 rs2 rd pack zbe zbf}
rv32i[zext_h] = { alu zbb zbp rs1 rs2 rd pack zbe zbf} # pack with rs2=x0
rv32i[pack{1-31}]= { alu zbp rs1 rs2 rd pack zbe zbf}
rv32i[mul] = { mul rs1 rs2 rd low } rv32i[mul] = { mul rs1 rs2 rd low }
rv32i[mulh] = { mul rs1 rs2 rd rs1_sign rs2_sign } rv32i[mulh] = { mul rs1 rs2 rd rs1_sign rs2_sign }
rv32i[mulhu] = { mul rs1 rs2 rd } rv32i[mulhu] = { mul rs1 rs2 rd }
rv32i[mulhsu] = { mul rs1 rs2 rd rs1_sign } rv32i[mulhsu] = { mul rs1 rs2 rd rs1_sign }
rv32i[bext] = { mul zbe rs1 rs2 rd bext } rv32i[bcompress] = { mul zbe rs1 rs2 rd bcompress }
rv32i[bdep] = { mul zbe rs1 rs2 rd bdep } rv32i[bdecompress] = { mul zbe rs1 rs2 rd bdecompress }
rv32i[clmul] = { mul zbc rs1 rs2 rd clmul } rv32i[clmul] = { mul zbc rs1 rs2 rd clmul }
rv32i[clmulh] = { mul zbc rs1 rs2 rd clmulh} rv32i[clmulh] = { mul zbc rs1 rs2 rd clmulh}
rv32i[clmulr] = { mul zbc rs1 rs2 rd clmulr} rv32i[clmulr] = { mul zbc rs1 rs2 rd clmulr}
@ -452,19 +485,16 @@ rv32i[bfp] = { mul zbf rs1 rs2 rd bfp }
rv32i[grev] = { mul zbp rs1 rs2 rd grev } rv32i[grev] = { mul zbp rs1 rs2 rd grev }
rv32i[grevi{0-23}] = { mul zbp rs1 rd shimm5 grev } rv32i[grevi{0-23}] = { mul zbp rs1 rd shimm5 grev }
rv32i[grevi{25-30}] = { mul zbp rs1 rd shimm5 grev } rv32i[grevi{25-31}] = { mul zbp rs1 rd shimm5 grev }
rv32i[rev8] = { alu zbb zbp rs1 rd shimm5 grev } # grevi24 rv32i[rev8] = { alu zbb zbp rs1 rd shimm5 grev } # grevi24
rv32i[rev] = { alu zbb zbp rs1 rd shimm5 grev } # grevi31
rv32i[gorc] = { mul zbp rs1 rs2 rd gorc } rv32i[gorc] = { mul zbp rs1 rs2 rd gorc }
rv32i[gorci{0-6}] = { mul zbp rs1 rd shimm5 gorc } rv32i[gorci{0-6}] = { mul zbp rs1 rd shimm5 gorc }
rv32i[gorci{8-15}] = { mul zbp rs1 rd shimm5 gorc } rv32i[gorci{8-31}] = { mul zbp rs1 rd shimm5 gorc }
rv32i[gorci{17-31}] = { mul zbp rs1 rd shimm5 gorc }
rv32i[orc_b] = { alu zbb zbp rs1 rd shimm5 gorc } # gorci7 rv32i[orc_b] = { alu zbb zbp rs1 rd shimm5 gorc } # gorci7
rv32i[orc16] = { alu zbb zbp rs1 rd shimm5 gorc } # gorci16
rv32i[shfl] = { mul zbp rs1 rs2 rd shfl } rv32i[shfl] = { mul zbp rs1 rs2 rd shfl }
@ -473,6 +503,11 @@ rv32i[shfli] = { mul zbp rs1 rd shimm5 shfl }
rv32i[unshfl] = { mul zbp rs1 rs2 rd unshfl} rv32i[unshfl] = { mul zbp rs1 rs2 rd unshfl}
rv32i[unshfli] = { mul zbp rs1 rd shimm5 unshfl} rv32i[unshfli] = { mul zbp rs1 rd shimm5 unshfl}
rv32i[xperm_n] = { mul zbp rs1 rs2 rd xperm_n}
rv32i[xperm_b] = { mul zbp rs1 rs2 rd xperm_b}
rv32i[xperm_h] = { mul zbp rs1 rs2 rd xperm_h}
rv32i[div] = { div rs1 rs2 rd } rv32i[div] = { div rs1 rs2 rd }
rv32i[divu] = { div rs1 rs2 rd unsign } rv32i[divu] = { div rs1 rs2 rd unsign }

285
design/dec/el2_dec_decode_ctl.sv
View File

@ -371,6 +371,8 @@ import el2_pkg::*;
logic bitmanip_zbf_legal; logic bitmanip_zbf_legal;
logic bitmanip_zba_legal; logic bitmanip_zba_legal;
logic bitmanip_zbb_zbp_legal; logic bitmanip_zbb_zbp_legal;
logic bitmanip_zbp_zbe_zbf_legal;
logic bitmanip_zbb_zbp_zbe_zbf_legal;
logic bitmanip_legal; logic bitmanip_legal;
logic data_gate_en; logic data_gate_en;
@ -563,15 +565,13 @@ end // else: !if(pt.BTB_ENABLE==1)
assign i0_ap.clz = i0_dp.clz; assign i0_ap.clz = i0_dp.clz;
assign i0_ap.ctz = i0_dp.ctz; assign i0_ap.ctz = i0_dp.ctz;
assign i0_ap.pcnt = i0_dp.pcnt; assign i0_ap.cpop = i0_dp.cpop;
assign i0_ap.sext_b = i0_dp.sext_b; assign i0_ap.sext_b = i0_dp.sext_b;
assign i0_ap.sext_h = i0_dp.sext_h; assign i0_ap.sext_h = i0_dp.sext_h;
assign i0_ap.sh1add = i0_dp.sh1add; assign i0_ap.sh1add = i0_dp.sh1add;
assign i0_ap.sh2add = i0_dp.sh2add; assign i0_ap.sh2add = i0_dp.sh2add;
assign i0_ap.sh3add = i0_dp.sh3add; assign i0_ap.sh3add = i0_dp.sh3add;
assign i0_ap.zba = i0_dp.zba; assign i0_ap.zba = i0_dp.zba;
assign i0_ap.slo = i0_dp.slo;
assign i0_ap.sro = i0_dp.sro;
assign i0_ap.min = i0_dp.min; assign i0_ap.min = i0_dp.min;
assign i0_ap.max = i0_dp.max; assign i0_ap.max = i0_dp.max;
assign i0_ap.pack = i0_dp.pack; assign i0_ap.pack = i0_dp.pack;
@ -582,10 +582,10 @@ end // else: !if(pt.BTB_ENABLE==1)
assign i0_ap.grev = i0_dp.grev; assign i0_ap.grev = i0_dp.grev;
assign i0_ap.gorc = i0_dp.gorc; assign i0_ap.gorc = i0_dp.gorc;
assign i0_ap.zbb = i0_dp.zbb; assign i0_ap.zbb = i0_dp.zbb;
assign i0_ap.sbset = i0_dp.sbset; assign i0_ap.bset = i0_dp.bset;
assign i0_ap.sbclr = i0_dp.sbclr; assign i0_ap.bclr = i0_dp.bclr;
assign i0_ap.sbinv = i0_dp.sbinv; assign i0_ap.binv = i0_dp.binv;
assign i0_ap.sbext = i0_dp.sbext; assign i0_ap.bext = i0_dp.bext;
assign i0_ap.csr_write = i0_csr_write_only_d; assign i0_ap.csr_write = i0_csr_write_only_d;
assign i0_ap.csr_imm = i0_dp.csr_imm; assign i0_ap.csr_imm = i0_dp.csr_imm;
@ -834,8 +834,8 @@ end : cam_array
assign mul_p.rs1_sign = i0_dp.rs1_sign; assign mul_p.rs1_sign = i0_dp.rs1_sign;
assign mul_p.rs2_sign = i0_dp.rs2_sign; assign mul_p.rs2_sign = i0_dp.rs2_sign;
assign mul_p.low = i0_dp.low; assign mul_p.low = i0_dp.low;
assign mul_p.bext = i0_dp.bext; assign mul_p.bcompress = i0_dp.bcompress;
assign mul_p.bdep = i0_dp.bdep; assign mul_p.bdecompress = i0_dp.bdecompress;
assign mul_p.clmul = i0_dp.clmul; assign mul_p.clmul = i0_dp.clmul;
assign mul_p.clmulh = i0_dp.clmulh; assign mul_p.clmulh = i0_dp.clmulh;
assign mul_p.clmulr = i0_dp.clmulr; assign mul_p.clmulr = i0_dp.clmulr;
@ -843,6 +843,9 @@ end : cam_array
assign mul_p.gorc = i0_dp.gorc; assign mul_p.gorc = i0_dp.gorc;
assign mul_p.shfl = i0_dp.shfl; assign mul_p.shfl = i0_dp.shfl;
assign mul_p.unshfl = i0_dp.unshfl; assign mul_p.unshfl = i0_dp.unshfl;
assign mul_p.xperm_n = i0_dp.xperm_n;
assign mul_p.xperm_b = i0_dp.xperm_b;
assign mul_p.xperm_h = i0_dp.xperm_h;
assign mul_p.crc32_b = i0_dp.crc32_b; assign mul_p.crc32_b = i0_dp.crc32_b;
assign mul_p.crc32_h = i0_dp.crc32_h; assign mul_p.crc32_h = i0_dp.crc32_h;
assign mul_p.crc32_w = i0_dp.crc32_w; assign mul_p.crc32_w = i0_dp.crc32_w;
@ -851,6 +854,7 @@ end : cam_array
assign mul_p.crc32c_w = i0_dp.crc32c_w; assign mul_p.crc32c_w = i0_dp.crc32c_w;
assign mul_p.bfp = i0_dp.bfp; assign mul_p.bfp = i0_dp.bfp;
always_comb begin always_comb begin
lsu_p = '0; lsu_p = '0;
@ -1077,7 +1081,7 @@ end : cam_array
if (pt.BITMANIP_ZBE == 1) if (pt.BITMANIP_ZBE == 1)
assign bitmanip_zbe_legal = 1'b1; assign bitmanip_zbe_legal = 1'b1;
else else
assign bitmanip_zbe_legal = ~i0_dp.zbe; assign bitmanip_zbe_legal = ~(i0_dp.zbe & ~i0_dp.zbp & ~i0_dp.zbf);
if (pt.BITMANIP_ZBC == 1) if (pt.BITMANIP_ZBC == 1)
assign bitmanip_zbc_legal = 1'b1; assign bitmanip_zbc_legal = 1'b1;
@ -1087,7 +1091,7 @@ end : cam_array
if (pt.BITMANIP_ZBP == 1) if (pt.BITMANIP_ZBP == 1)
assign bitmanip_zbp_legal = 1'b1; assign bitmanip_zbp_legal = 1'b1;
else else
assign bitmanip_zbp_legal = ~(i0_dp.zbp & ~i0_dp.zbb); assign bitmanip_zbp_legal = ~(i0_dp.zbp & ~i0_dp.zbb & ~i0_dp.zbe & ~i0_dp.zbf);
if (pt.BITMANIP_ZBR == 1) if (pt.BITMANIP_ZBR == 1)
assign bitmanip_zbr_legal = 1'b1; assign bitmanip_zbr_legal = 1'b1;
@ -1097,7 +1101,7 @@ end : cam_array
if (pt.BITMANIP_ZBF == 1) if (pt.BITMANIP_ZBF == 1)
assign bitmanip_zbf_legal = 1'b1; assign bitmanip_zbf_legal = 1'b1;
else else
assign bitmanip_zbf_legal = ~i0_dp.zbf; assign bitmanip_zbf_legal = ~(i0_dp.zbf & ~i0_dp.zbp & ~i0_dp.zbe);
if (pt.BITMANIP_ZBA == 1) if (pt.BITMANIP_ZBA == 1)
assign bitmanip_zba_legal = 1'b1; assign bitmanip_zba_legal = 1'b1;
@ -1107,11 +1111,21 @@ end : cam_array
if ( (pt.BITMANIP_ZBB == 1) | (pt.BITMANIP_ZBP == 1) ) if ( (pt.BITMANIP_ZBB == 1) | (pt.BITMANIP_ZBP == 1) )
assign bitmanip_zbb_zbp_legal = 1'b1; assign bitmanip_zbb_zbp_legal = 1'b1;
else else
assign bitmanip_zbb_zbp_legal = ~(i0_dp.zbb & i0_dp.zbp); assign bitmanip_zbb_zbp_legal = ~(i0_dp.zbb & i0_dp.zbp & ~i0_dp.zbf); // added ~ZBF to exclude ZEXT.H
if ( (pt.BITMANIP_ZBP == 1) | (pt.BITMANIP_ZBE == 1) | (pt.BITMANIP_ZBF == 1))
assign bitmanip_zbp_zbe_zbf_legal = 1'b1;
else
assign bitmanip_zbp_zbe_zbf_legal = ~(i0_dp.zbp & i0_dp.zbe & i0_dp.zbf & ~i0_dp.zbb); // added ~ZBB to exclude ZEXT.H
if ( (pt.BITMANIP_ZBB == 1) | (pt.BITMANIP_ZBP == 1) | (pt.BITMANIP_ZBE == 1) | (pt.BITMANIP_ZBF == 1))
assign bitmanip_zbb_zbp_zbe_zbf_legal = 1'b1;
else
assign bitmanip_zbb_zbp_zbe_zbf_legal = ~(i0_dp.zbp & i0_dp.zbe & i0_dp.zbf & i0_dp.zbb); // added only for ZEXT.H
assign any_csr_d = i0_dp.csr_read | i0_csr_write; assign any_csr_d = i0_dp.csr_read | i0_csr_write;
assign bitmanip_legal = bitmanip_zbb_legal & bitmanip_zbs_legal & bitmanip_zbe_legal & bitmanip_zbc_legal & bitmanip_zbp_legal & bitmanip_zbr_legal & bitmanip_zbf_legal & bitmanip_zba_legal & bitmanip_zbb_zbp_legal; assign bitmanip_legal = bitmanip_zbb_legal & bitmanip_zbs_legal & bitmanip_zbe_legal & bitmanip_zbc_legal & bitmanip_zbp_legal & bitmanip_zbr_legal & bitmanip_zbf_legal & bitmanip_zba_legal & bitmanip_zbb_zbp_legal & bitmanip_zbp_zbe_zbf_legal & bitmanip_zbb_zbp_zbe_zbf_legal;
assign i0_legal = i0_dp.legal & (~any_csr_d | dec_csr_legal_d) & bitmanip_legal; assign i0_legal = i0_dp.legal & (~any_csr_d | dec_csr_legal_d) & bitmanip_legal;
@ -1505,21 +1519,19 @@ import el2_pkg::*;
assign i[31:0] = inst[31:0]; assign i[31:0] = inst[31:0];
assign out.alu = (i[30]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[14]&!i[5]&i[4]) | (i[30]
&!i[27]&!i[24]&i[4]) | (!i[30]&!i[25]&i[13]&i[12]) | (!i[29]&!i[27]
&!i[5]&i[4]) | (i[27]&i[25]&i[14]&i[4]) | (!i[29]&!i[25]&!i[13]&!i[12]
&i[4]) | (i[29]&i[27]&!i[14]&i[12]&i[4]) | (!i[27]&i[14]&!i[5]&i[4]) | (
i[30]&!i[29]&!i[13]&i[4]) | (!i[27]&!i[25]&i[5]&i[4]) | (i[13]&!i[5]
&i[4]) | (i[2]) | (i[6]) | (!i[30]&i[29]&!i[24]&!i[23]&i[22]&i[21]
&i[20]&!i[5]&i[4]) | (!i[12]&!i[5]&i[4]);
assign out.alu = (i[30]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[14]&!i[5]&i[4]) | (i[29] assign out.rs1 = (!i[13]&i[11]&!i[2]) | (!i[13]&i[10]&!i[2]) | (i[19]&i[13]&!i[2]) | (
&!i[27]&!i[24]&i[4]) | (!i[25]&!i[13]&!i[12]&i[4]) | (!i[30]&!i[25] !i[13]&i[9]&!i[2]) | (i[18]&i[13]&!i[2]) | (!i[13]&i[8]&!i[2]) | (
&i[13]&i[12]) | (i[27]&i[25]&i[14]&i[4]) | (i[29]&i[27]&!i[14]&i[4]) | ( i[17]&i[13]&!i[2]) | (!i[13]&i[7]&!i[2]) | (i[16]&i[13]&!i[2]) | (
i[29]&!i[14]&i[5]&i[4]) | (!i[27]&!i[25]&i[14]&i[4]) | (i[30]&!i[29] i[15]&i[13]&!i[2]) | (!i[4]&!i[2]) | (!i[14]&!i[13]&i[6]&!i[3]) | (
&!i[13]&i[4]) | (!i[30]&!i[27]&!i[25]&i[4]) | (i[13]&!i[5]&i[4]) | ( !i[6]&!i[2]);
!i[12]&!i[5]&i[4]) | (i[2]) | (i[6]) | (i[30]&i[24]&i[23]&i[22]&i[21]
&i[20]&!i[5]&i[4]) | (!i[30]&i[29]&!i[24]&!i[23]&i[22]&i[21]&i[20]
&!i[5]&i[4]) | (!i[30]&i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[5]&i[4]);
assign out.rs1 = (!i[14]&!i[13]&!i[2]) | (!i[13]&i[11]&!i[2]) | (i[19]&i[13]&!i[2]) | (
!i[13]&i[10]&!i[2]) | (i[18]&i[13]&!i[2]) | (!i[13]&i[9]&!i[2]) | (
i[17]&i[13]&!i[2]) | (!i[13]&i[8]&!i[2]) | (i[16]&i[13]&!i[2]) | (
!i[13]&i[7]&!i[2]) | (i[15]&i[13]&!i[2]) | (!i[4]&!i[3]) | (!i[6]
&!i[2]);
assign out.rs2 = (i[5]&!i[4]&!i[2]) | (!i[6]&i[5]&!i[2]); assign out.rs2 = (i[5]&!i[4]&!i[2]) | (!i[6]&i[5]&!i[2]);
@ -1528,7 +1540,7 @@ assign out.imm12 = (!i[4]&!i[3]&i[2]) | (i[13]&!i[5]&i[4]&!i[2]) | (!i[13]&!i[12
assign out.rd = (!i[5]&!i[2]) | (i[5]&i[2]) | (i[4]); assign out.rd = (!i[5]&!i[2]) | (i[5]&i[2]) | (i[4]);
assign out.shimm5 = (i[27]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (!i[30]&!i[13]&i[12] assign out.shimm5 = (!i[29]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&!i[13]&i[12]
&!i[5]&i[4]&!i[2]) | (i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); &!i[5]&i[4]&!i[2]) | (i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
assign out.imm20 = (i[5]&i[3]) | (i[4]&i[2]); assign out.imm20 = (i[5]&i[3]) | (i[4]&i[2]);
@ -1562,15 +1574,14 @@ assign out.sll = (!i[29]&!i[27]&!i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
assign out.sra = (i[30]&!i[29]&!i[27]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); assign out.sra = (i[30]&!i[29]&!i[27]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
assign out.srl = (!i[30]&!i[29]&!i[27]&!i[25]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); assign out.srl = (!i[30]&!i[27]&!i[25]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
assign out.slt = (!i[29]&!i[25]&!i[14]&i[13]&!i[6]&i[4]&!i[2]) | (!i[14]&i[13]&!i[5] assign out.slt = (!i[29]&!i[25]&!i[14]&i[13]&!i[6]&i[4]&!i[2]) | (!i[14]&i[13]&!i[5]
&i[4]&!i[2]); &i[4]&!i[2]);
assign out.unsign = (!i[27]&i[25]&i[14]&i[12]&!i[6]&i[5]&!i[2]) | (!i[14]&i[13] assign out.unsign = (!i[14]&i[13]&i[12]&!i[5]&!i[2]) | (i[13]&i[6]&!i[4]&!i[2]) | (
&i[12]&!i[5]&!i[2]) | (i[13]&i[6]&!i[4]&!i[2]) | (i[14]&!i[5]&!i[4]) | ( i[14]&!i[5]&!i[4]) | (!i[25]&!i[14]&i[13]&i[12]&!i[6]&!i[2]) | (
!i[25]&!i[14]&i[13]&i[12]&!i[6]&!i[2]) | (i[27]&i[25]&i[14]&i[13] i[25]&i[14]&i[12]&!i[6]&i[5]&!i[2]);
&!i[6]&i[5]&!i[2]);
assign out.condbr = (i[6]&!i[4]&!i[2]); assign out.condbr = (i[6]&!i[4]&!i[2]);
@ -1625,19 +1636,17 @@ assign out.ecall = (!i[21]&!i[20]&!i[13]&!i[12]&i[6]&i[4]);
assign out.mret = (i[29]&!i[13]&!i[12]&i[6]&i[4]); assign out.mret = (i[29]&!i[13]&!i[12]&i[6]&i[4]);
assign out.mul = (!i[30]&i[27]&i[24]&i[20]&i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | ( assign out.mul = (i[29]&!i[27]&i[24]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[30]
i[29]&i[27]&!i[24]&i[23]&i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | ( &i[27]&i[13]&!i[6]&i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[23]&!i[20]
i[29]&i[27]&!i[24]&!i[20]&i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | ( &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[21]&i[20]
i[27]&!i[25]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | (i[30]&i[27]&i[13] &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&i[24]&i[21]
&!i[6]&i[5]&i[4]&!i[2]) | (i[29]&i[27]&i[22]&!i[20]&i[14]&!i[13] &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[24]&!i[22]
&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[21]&i[20]&i[14]&!i[13] &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (!i[30]&i[29]&i[23]&i[14]
&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[22]&i[21]&i[14]&!i[13] &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[30]&i[29]&i[27]&i[22]&i[14]
&i[12]&!i[5]&i[4]&!i[2]) | (i[30]&i[29]&i[27]&!i[23]&i[14]&!i[13] &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&!i[25]&i[13]&!i[12]&!i[6]
&i[12]&!i[5]&i[4]&!i[2]) | (!i[30]&i[27]&i[23]&i[14]&!i[13]&i[12] &i[5]&i[4]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&i[12]&!i[6]
&!i[5]&i[4]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&i[12]&!i[6] &i[4]&!i[2]) | (i[25]&!i[14]&!i[6]&i[5]&i[4]&!i[2]) | (i[29]&i[27]
&i[4]&!i[2]) | (i[25]&!i[14]&!i[6]&i[5]&i[4]&!i[2]) | (i[30]&!i[27] &i[14]&!i[6]&i[5]&!i[2]);
&i[24]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&i[14]
&!i[6]&i[5]&!i[2]);
assign out.rs1_sign = (!i[27]&i[25]&!i[14]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | ( assign out.rs1_sign = (!i[27]&i[25]&!i[14]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | (
!i[27]&i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); !i[27]&i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
@ -1654,169 +1663,173 @@ assign out.fence = (!i[5]&i[3]);
assign out.fence_i = (i[12]&!i[5]&i[3]); assign out.fence_i = (i[12]&!i[5]&i[3]);
assign out.clz = (i[30]&!i[27]&!i[24]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5] assign out.clz = (i[29]&!i[27]&!i[24]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]
&i[4]&!i[2]); &i[4]&!i[2]);
assign out.ctz = (i[30]&!i[27]&!i[24]&!i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4] assign out.ctz = (i[29]&!i[27]&!i[24]&!i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]
&!i[2]); &!i[2]);
assign out.pcnt = (i[30]&!i[27]&!i[24]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); assign out.cpop = (i[29]&!i[27]&!i[24]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
assign out.sext_b = (i[30]&!i[27]&i[22]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); assign out.sext_b = (i[29]&!i[27]&i[22]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
assign out.sext_h = (i[30]&!i[27]&i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); assign out.sext_h = (i[29]&!i[27]&i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
assign out.slo = (!i[30]&i[29]&!i[27]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); assign out.min = (i[27]&i[25]&i[14]&!i[13]&!i[6]&i[5]&!i[2]);
assign out.sro = (!i[30]&i[29]&!i[27]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); assign out.max = (i[27]&i[25]&i[14]&i[13]&!i[6]&i[5]&!i[2]);
assign out.min = (i[27]&i[25]&i[14]&!i[12]&!i[6]&i[5]&!i[2]); assign out.pack = (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]);
assign out.max = (i[27]&i[25]&i[14]&i[12]&!i[6]&i[5]&!i[2]);
assign out.pack = (!i[30]&i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]);
assign out.packu = (i[30]&i[27]&!i[13]&!i[12]&i[5]&i[4]&!i[2]); assign out.packu = (i[30]&i[27]&!i[13]&!i[12]&i[5]&i[4]&!i[2]);
assign out.packh = (!i[30]&i[27]&!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]); assign out.packh = (!i[30]&i[27]&!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]);
assign out.rol = (i[30]&!i[27]&!i[14]&i[12]&!i[6]&i[5]&i[4]&!i[2]); assign out.rol = (i[29]&!i[27]&!i[14]&i[12]&!i[6]&i[5]&i[4]&!i[2]);
assign out.ror = (i[30]&i[29]&!i[27]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); assign out.ror = (i[29]&!i[27]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
assign out.zbb = (i[30]&!i[27]&!i[24]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | ( assign out.zbb = (!i[30]&!i[29]&i[27]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[13]
!i[30]&i[27]&i[14]&i[13]&i[12]&!i[6]&i[5]&!i[2]) | (i[30]&i[29]&!i[27] &!i[12]&i[5]&i[4]&!i[2]) | (i[29]&!i[27]&!i[24]&!i[13]&i[12]&!i[5]
&i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&!i[13]&!i[12]&i[5] &i[4]&!i[2]) | (i[29]&!i[27]&i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (
&i[4]&!i[2]) | (i[30]&i[14]&!i[13]&!i[12]&!i[6]&i[5]&!i[2]) | (i[30] i[30]&!i[27]&i[14]&!i[12]&!i[6]&i[5]&!i[2]) | (i[30]&!i[27]&i[13]
&!i[27]&i[13]&!i[6]&i[5]&i[4]&!i[2]) | (i[30]&i[29]&!i[27]&!i[6]&i[5] &!i[6]&i[5]&i[4]&!i[2]) | (i[29]&!i[27]&i[12]&!i[6]&i[5]&i[4]&!i[2]) | (
&i[4]&!i[2]) | (i[30]&i[29]&i[24]&i[23]&i[22]&i[21]&i[20]&i[14]&!i[13] !i[30]&i[29]&!i[24]&!i[23]&i[22]&i[21]&i[20]&i[14]&!i[13]&i[12]&!i[5]
&i[12]&!i[5]&i[4]&!i[2]) | (!i[30]&i[29]&i[27]&!i[24]&!i[23]&i[22] &i[4]&!i[2]) | (i[30]&i[29]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[14]
&i[21]&i[20]&i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (!i[30]&i[27] &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]);
&i[24]&!i[23]&!i[22]&!i[21]&!i[20]&i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (
i[30]&i[29]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[14]&!i[13]&i[12]&!i[5]
&i[4]&!i[2]) | (i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]);
assign out.sbset = (!i[30]&i[29]&i[27]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); assign out.bset = (!i[30]&i[29]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
assign out.sbclr = (i[30]&!i[29]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); assign out.bclr = (i[30]&!i[29]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
assign out.sbinv = (i[30]&i[29]&i[27]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); assign out.binv = (i[30]&i[29]&i[27]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
assign out.sbext = (i[30]&!i[29]&i[27]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); assign out.bext = (i[30]&!i[29]&i[27]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
assign out.zbs = (i[29]&i[27]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]) | (i[30]&!i[29] assign out.zbs = (i[29]&i[27]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]) | (i[30]&!i[29]
&i[27]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); &i[27]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
assign out.bext = (!i[30]&i[27]&!i[25]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); assign out.bcompress = (!i[30]&!i[29]&i[27]&!i[25]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]);
assign out.bdep = (i[30]&i[27]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); assign out.bdecompress = (i[30]&i[27]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]);
assign out.zbe = (i[27]&!i[25]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); assign out.zbe = (i[30]&i[27]&i[14]&i[13]&!i[12]&!i[6]&i[5]&!i[2]) | (!i[30]&i[27]
&!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]
&!i[12]&!i[6]&i[5]&i[4]&!i[2]);
assign out.clmul = (i[27]&i[25]&!i[14]&!i[13]&!i[6]&i[5]&i[4]&!i[2]); assign out.clmul = (i[27]&i[25]&!i[14]&!i[13]&!i[6]&i[5]&i[4]&!i[2]);
assign out.clmulh = (i[27]&!i[14]&i[13]&i[12]&!i[6]&i[5]&!i[2]); assign out.clmulh = (i[27]&!i[14]&i[13]&i[12]&!i[6]&i[5]&!i[2]);
assign out.clmulr = (i[27]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); assign out.clmulr = (i[27]&i[25]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]);
assign out.zbc = (i[27]&i[25]&!i[14]&!i[6]&i[5]&i[4]&!i[2]); assign out.zbc = (i[27]&i[25]&!i[14]&!i[6]&i[5]&i[4]&!i[2]);
assign out.grev = (i[30]&i[29]&i[27]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); assign out.grev = (i[30]&i[29]&i[27]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
assign out.gorc = (!i[30]&i[29]&i[27]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); assign out.gorc = (!i[30]&i[29]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
assign out.shfl = (!i[30]&!i[29]&i[27]&!i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); assign out.shfl = (!i[30]&!i[29]&i[27]&!i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
assign out.unshfl = (!i[30]&!i[29]&i[27]&!i[25]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); assign out.unshfl = (!i[30]&!i[29]&i[27]&!i[25]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
assign out.zbp = (!i[30]&i[29]&!i[27]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (!i[30]&!i[29] assign out.xperm_n = (i[29]&i[27]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]);
&i[27]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[30]&!i[27]&i[13]&!i[6]
&i[5]&i[4]&!i[2]) | (i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (
i[30]&i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (i[29]&!i[27]&i[12]&!i[6]
&i[5]&i[4]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]&i[12]&!i[6]&i[5]&i[4]
&!i[2]) | (i[29]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
assign out.crc32_b = (i[30]&!i[27]&i[24]&!i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12] assign out.xperm_b = (i[29]&i[27]&!i[13]&!i[12]&i[5]&i[4]&!i[2]);
assign out.xperm_h = (i[29]&i[27]&i[14]&i[13]&!i[6]&i[5]&!i[2]);
assign out.zbp = (i[30]&!i[27]&!i[14]&i[12]&!i[6]&i[5]&i[4]&!i[2]) | (!i[30]&i[27]
&!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]) | (i[30]&!i[27]&i[13]&!i[6]
&i[5]&i[4]&!i[2]) | (i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (
i[30]&i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[12]&!i[6]
&i[5]&i[4]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&i[12]&!i[6]
&i[4]&!i[2]) | (i[29]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
assign out.crc32_b = (i[29]&!i[27]&i[24]&!i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]
&!i[5]&i[4]&!i[2]); &!i[5]&i[4]&!i[2]);
assign out.crc32_h = (i[30]&!i[27]&i[24]&!i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4] assign out.crc32_h = (i[29]&!i[27]&i[24]&!i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]
&!i[2]); &!i[2]);
assign out.crc32_w = (i[30]&!i[27]&i[24]&!i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4] assign out.crc32_w = (i[29]&!i[27]&i[24]&!i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]
&!i[2]); &!i[2]);
assign out.crc32c_b = (i[30]&!i[27]&i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5] assign out.crc32c_b = (i[29]&!i[27]&i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]
&i[4]&!i[2]); &i[4]&!i[2]);
assign out.crc32c_h = (i[30]&!i[27]&i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); assign out.crc32c_h = (i[29]&!i[27]&i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
assign out.crc32c_w = (i[30]&!i[27]&i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); assign out.crc32c_w = (i[29]&!i[27]&i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
assign out.zbr = (i[30]&!i[27]&i[24]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); assign out.zbr = (i[29]&!i[27]&i[24]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
assign out.bfp = (i[30]&i[27]&i[13]&i[12]&!i[6]&i[5]&!i[2]); assign out.bfp = (i[30]&i[27]&i[13]&i[12]&!i[6]&i[5]&!i[2]);
assign out.zbf = (i[30]&i[27]&i[13]&i[12]&!i[6]&i[5]&!i[2]); assign out.zbf = (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (
i[27]&!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]);
assign out.sh1add = (i[29]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); assign out.sh1add = (i[29]&!i[27]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]);
assign out.sh2add = (i[29]&i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]); assign out.sh2add = (i[29]&!i[27]&i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]);
assign out.sh3add = (i[29]&i[14]&i[13]&!i[6]&i[5]&!i[2]); assign out.sh3add = (i[29]&!i[27]&i[14]&i[13]&!i[6]&i[5]&!i[2]);
assign out.zba = (i[29]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); assign out.zba = (i[29]&!i[27]&!i[12]&!i[6]&i[5]&i[4]&!i[2]);
assign out.pm_alu = (i[28]&i[22]&!i[13]&!i[12]&i[4]) | (!i[30]&!i[29]&!i[27]&!i[25] assign out.pm_alu = (i[28]&i[20]&!i[13]&!i[12]&i[4]) | (!i[30]&!i[29]&!i[27]&!i[25]
&!i[6]&i[4]) | (!i[29]&!i[27]&!i[25]&!i[13]&i[12]&!i[6]&i[4]) | ( &!i[6]&i[4]) | (!i[29]&!i[27]&!i[25]&!i[13]&i[12]&!i[6]&i[4]) | (
!i[29]&!i[27]&!i[25]&!i[14]&!i[6]&i[4]) | (i[13]&!i[5]&i[4]) | (i[4] !i[29]&!i[27]&!i[25]&!i[14]&!i[6]&i[4]) | (i[13]&!i[5]&i[4]) | (i[4]
&i[2]) | (!i[12]&!i[5]&i[4]); &i[2]) | (!i[12]&!i[5]&i[4]);
assign out.legal = (!i[31]&!i[30]&!i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23] assign out.legal = (!i[31]&!i[30]&i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]
&i[22]&!i[21]&i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11] &!i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]
&!i[10]&!i[9]&!i[8]&!i[7]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | ( &!i[10]&!i[9]&!i[8]&!i[7]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (
!i[31]&!i[30]&i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&!i[22] !i[31]&!i[30]&!i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&i[22]
&i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]&!i[10] &!i[21]&i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]&!i[10]
&!i[9]&!i[8]&!i[7]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31] &!i[9]&!i[8]&!i[7]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]
&!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21] &!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]
&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]&!i[10]&!i[9]&!i[8] &!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]&!i[10]&!i[9]&!i[8]
&!i[7]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&i[29]&!i[28]&!i[26] &!i[7]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[28]
&!i[25]&i[24]&!i[22]&!i[20]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | ( &!i[26]&!i[25]&i[24]&!i[22]&!i[20]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (
!i[31]&i[29]&!i[28]&!i[26]&!i[25]&i[24]&!i[22]&!i[21]&!i[6]&!i[5] !i[31]&i[30]&i[29]&!i[28]&!i[26]&!i[25]&i[24]&!i[22]&!i[21]&!i[6]
&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&i[29]&!i[28]&!i[26]&!i[25]&!i[23] &!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[28]&!i[26]
&!i[22]&!i[20]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&i[29] &!i[25]&!i[23]&!i[22]&!i[20]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (
&!i[28]&!i[26]&!i[25]&!i[24]&!i[23]&!i[21]&!i[6]&!i[5]&i[4]&!i[3] !i[31]&i[30]&i[29]&!i[28]&!i[26]&!i[25]&!i[24]&!i[23]&!i[21]&!i[6]
&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]&!i[26]&i[25]&i[13]&!i[6] &!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]&!i[26]
&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]&!i[28]&!i[26]&!i[25]&!i[24] &i[25]&i[13]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[28]&i[27]&!i[26]
&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]&!i[28]&!i[27] &!i[25]&!i[24]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]
&!i[26]&!i[25]&i[14]&!i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31] &i[29]&!i[28]&!i[26]&!i[25]&i[13]&!i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (
&!i[30]&!i[28]&!i[27]&!i[26]&!i[25]&i[13]&!i[12]&!i[6]&i[4]&!i[3] !i[31]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[13]&!i[12]&!i[6]&i[4]
&i[1]&i[0]) | (!i[31]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[13]&!i[12] &!i[3]&i[1]&i[0]) | (!i[31]&i[30]&!i[28]&!i[26]&!i[25]&i[14]&!i[6]
&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[28]&!i[27]&!i[26]&!i[25] &!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]&!i[26]
&i[14]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29] &!i[13]&i[12]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]
&!i[28]&!i[26]&!i[13]&i[12]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | ( &!i[28]&!i[27]&!i[26]&!i[25]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]
&i[30]&i[29]&!i[28]&!i[26]&!i[25]&!i[13]&i[12]&i[5]&i[4]&!i[3]&!i[2]
&i[1]&i[0]) | (!i[31]&i[30]&!i[28]&i[27]&!i[26]&!i[25]&!i[13]&i[12]
&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[29]&!i[28]&!i[26]&!i[25]
&i[14]&!i[6]&i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&i[29]&!i[28]&i[27]
&!i[26]&!i[25]&!i[13]&i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]
&!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[6]&i[5]&i[4]&!i[3]&i[1]&i[0]) | (
!i[31]&!i[30]&!i[29]&!i[28]&!i[26]&i[14]&!i[6]&i[5]&i[4]&!i[3]&i[1] !i[31]&!i[30]&!i[29]&!i[28]&!i[26]&i[14]&!i[6]&i[5]&i[4]&!i[3]&i[1]
&i[0]) | (!i[31]&i[30]&!i[28]&i[27]&!i[26]&!i[25]&!i[13]&i[12]&!i[6] &i[0]) | (!i[14]&!i[13]&!i[12]&i[6]&i[5]&!i[4]&!i[3]&i[1]&i[0]) | (
&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&i[29]&!i[28]&i[27]&!i[26]&!i[25] i[14]&i[6]&i[5]&!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[14]&!i[13]&i[5]
&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]&!i[28]&!i[27] &!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[12]&!i[6]&!i[5]&i[4]&!i[3]&i[1]
&!i[26]&!i[25]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30] &i[0]) | (!i[13]&i[12]&i[6]&i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]
&!i[29]&!i[28]&!i[27]&!i[26]&!i[6]&i[5]&i[4]&!i[3]&i[1]&i[0]) | ( &!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]
!i[14]&!i[13]&!i[12]&i[6]&i[5]&!i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[29] &!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&!i[11]&!i[10]
&!i[28]&!i[26]&!i[25]&i[14]&!i[6]&i[5]&i[4]&!i[3]&i[1]&i[0]) | ( &!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[31]
!i[31]&i[29]&!i[28]&!i[26]&!i[25]&!i[13]&i[12]&i[5]&i[4]&!i[3]&!i[2] &!i[30]&!i[29]&!i[28]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]
&i[1]&i[0]) | (i[14]&i[6]&i[5]&!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[14] &!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&i[3]&i[2]
&!i[13]&i[5]&!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[12]&!i[6]&!i[5]&i[4] &i[1]&i[0]) | (i[13]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]
&!i[3]&i[1]&i[0]) | (!i[13]&i[12]&i[6]&i[5]&!i[3]&!i[2]&i[1]&i[0]) | ( &!i[30]&!i[28]&!i[26]&!i[25]&i[14]&!i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (
!i[31]&!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&!i[22]
&!i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&!i[11]
&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (
!i[31]&!i[30]&!i[29]&!i[28]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]
&!i[13]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&i[3]
&i[2]&i[1]&i[0]) | (i[13]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (
i[6]&i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[14]&!i[12]&!i[6]&!i[4] i[6]&i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[14]&!i[12]&!i[6]&!i[4]
&!i[3]&!i[2]&i[1]&i[0]) | (!i[13]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1] &!i[3]&!i[2]&i[1]&i[0]) | (!i[13]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]
&i[0]) | (i[13]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[6]&i[4]&!i[3] &i[0]) | (i[13]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[6]&i[4]&!i[3]
&i[2]&i[1]&i[0]); &i[2]&i[1]&i[0]);
endmodule // el2_dec_dec_ctl endmodule // el2_dec_dec_ctl

16
design/dec/el2_dec_tlu_ctl.sv
View File

@ -604,8 +604,8 @@ localparam DCSR_STEP = 2;
assign debug_brkpt_status_ns = (debug_brkpt_valid | debug_brkpt_status_f) & (internal_dbg_halt_mode & ~dcsr_single_step_running_f); assign debug_brkpt_status_ns = (debug_brkpt_valid | debug_brkpt_status_f) & (internal_dbg_halt_mode & ~dcsr_single_step_running_f);
// acks back to interface // acks back to interface
assign mpc_debug_halt_ack_ns = mpc_halt_state_f & internal_dbg_halt_mode_f & mpc_debug_halt_req_sync & core_empty; assign mpc_debug_halt_ack_ns = (mpc_halt_state_f & internal_dbg_halt_mode_f & mpc_debug_halt_req_sync & core_empty) | (mpc_debug_halt_ack_f & mpc_debug_halt_req_sync);
assign mpc_debug_run_ack_ns = (mpc_debug_run_req_sync & ~dbg_halt_state_ns & ~mpc_debug_halt_req_sync) | (mpc_debug_run_ack_f & mpc_debug_run_req_sync) ; assign mpc_debug_run_ack_ns = (mpc_debug_run_req_sync & ~internal_dbg_halt_mode & ~mpc_debug_halt_req_sync) | (mpc_debug_run_ack_f & mpc_debug_run_req_sync) ;
// Pins // Pins
assign mpc_debug_halt_ack = mpc_debug_halt_ack_f; assign mpc_debug_halt_ack = mpc_debug_halt_ack_f;
@ -2595,12 +2595,14 @@ assign csr_dicago = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3]
assign presync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] assign presync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]
&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7] &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]
&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[6] &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[5]
&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]
&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[6]
&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]
&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11] &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]
&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]
&!dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4] &!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4]
&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | ( &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (
dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]
&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]); &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]);
@ -2727,7 +2729,7 @@ assign dec_csr_legal_d = ( dec_csr_any_unq_d &
assign dec_csr_rddata_d[31:0] = ( ({32{csr_misa}} & 32'h40001104) | assign dec_csr_rddata_d[31:0] = ( ({32{csr_misa}} & 32'h40001104) |
({32{csr_mvendorid}} & 32'h00000045) | ({32{csr_mvendorid}} & 32'h00000045) |
({32{csr_marchid}} & 32'h00000010) | ({32{csr_marchid}} & 32'h00000010) |
({32{csr_mimpid}} & 32'h3) | ({32{csr_mimpid}} & 32'h4) |
({32{csr_mhartid}} & {core_id[31:4], 4'b0}) | ({32{csr_mhartid}} & {core_id[31:4], 4'b0}) |
({32{csr_mstatus}} & {19'b0, 2'b11, 3'b0, mstatus[1], 3'b0, mstatus[0], 3'b0}) | ({32{csr_mstatus}} & {19'b0, 2'b11, 3'b0, mstatus[1], 3'b0, mstatus[0], 3'b0}) |
({32{csr_mtvec}} & {mtvec[30:1], 1'b0, mtvec[0]}) | ({32{csr_mtvec}} & {mtvec[30:1], 1'b0, mtvec[0]}) |

2
design/el2_dma_ctrl.sv
View File

@ -318,7 +318,7 @@ module el2_dma_ctrl #(
//Dbg outputs //Dbg outputs
assign dma_dbg_ready = fifo_empty & dbg_dma_bubble; assign dma_dbg_ready = fifo_empty & dbg_dma_bubble;
assign dma_dbg_cmd_done = (fifo_valid[RspPtr] & fifo_dbg[RspPtr] & fifo_done[RspPtr]); assign dma_dbg_cmd_done = (fifo_valid[RspPtr] & fifo_dbg[RspPtr] & fifo_done[RspPtr]);
assign dma_dbg_cmd_fail = |fifo_error[RspPtr]; assign dma_dbg_cmd_fail = (|fifo_error[RspPtr] & dma_dbg_cmd_done) ;
assign dma_dbg_sz[1:0] = fifo_sz[RspPtr][1:0]; assign dma_dbg_sz[1:0] = fifo_sz[RspPtr][1:0];
assign dma_dbg_addr[1:0] = fifo_addr[RspPtr][1:0]; assign dma_dbg_addr[1:0] = fifo_addr[RspPtr][1:0];

64
design/el2_pic_ctrl.sv
View File

@ -196,7 +196,15 @@ rvdff #(1) picm_rde_flop (.*, .din (picm_rden), .dout(picm_rden_ff),
rvdff #(1) picm_mke_flop (.*, .din (picm_mken), .dout(picm_mken_ff), .clk(free_clk)); rvdff #(1) picm_mke_flop (.*, .din (picm_mken), .dout(picm_mken_ff), .clk(free_clk));
rvdff #(32) picm_dat_flop (.*, .din (picm_wr_data[31:0]), .dout(picm_wr_data_ff[31:0]), .clk(pic_data_c1_clk)); rvdff #(32) picm_dat_flop (.*, .din (picm_wr_data[31:0]), .dout(picm_wr_data_ff[31:0]), .clk(pic_data_c1_clk));
//rvsyncss #(pt.PIC_TOTAL_INT_PLUS1-1) sync_inst
//(
// .clk (free_clk),
// .dout(extintsrc_req_sync[pt.PIC_TOTAL_INT_PLUS1-1:1]),
// .din (extintsrc_req[pt.PIC_TOTAL_INT_PLUS1-1:1]),
// .*) ;
//
//assign extintsrc_req_sync[0] = extintsrc_req[0];
/*
genvar p ; genvar p ;
for (p=0; p<=INT_ENABLE_GRPS ; p++) begin : IO_CLK_GRP for (p=0; p<=INT_ENABLE_GRPS ; p++) begin : IO_CLK_GRP
if (p==INT_ENABLE_GRPS) begin : LAST_GRP if (p==INT_ENABLE_GRPS) begin : LAST_GRP
@ -207,10 +215,45 @@ for (p=0; p<=INT_ENABLE_GRPS ; p++) begin : IO_CLK_GRP
rvoclkhdr intenable_c1_cgc ( .en(intenable_clk_enable_grp[p]), .l1clk(gw_clk[p]), .* ); rvoclkhdr intenable_c1_cgc ( .en(intenable_clk_enable_grp[p]), .l1clk(gw_clk[p]), .* );
end end
end end
*/
genvar i ; genvar i ;
genvar p ;
for (p=0; p<=INT_ENABLE_GRPS ; p++) begin : IO_CLK_GRP
wire grp_clk, grp_clken;
assign grp_clken = |intenable_clk_enable[(p==INT_ENABLE_GRPS?pt.PIC_TOTAL_INT_PLUS1-1:p*4+3) : p*4] | io_clk_override;
`ifndef RV_FPGA_OPTIMIZE
rvclkhdr intenable_c1_cgc( .en(grp_clken), .l1clk(grp_clk), .* );
`else
assign gw_clk[p] = 1'b0 ;
`endif
for(genvar i= (p==0 ? 1: 0); i< (p==INT_ENABLE_GRPS ? pt.PIC_TOTAL_INT_PLUS1-p*4 :4); i++) begin : GW
el2_configurable_gw gw_inst(
.*,
.gw_clk(grp_clk),
.rawclk(clk),
.clken (grp_clken),
.extintsrc_req(extintsrc_req[i+p*4]) ,
.meigwctrl_polarity(gw_config_reg[i+p*4][0]) ,
.meigwctrl_type(gw_config_reg[i+p*4][1]) ,
.meigwclr(gw_clear_reg_we[i+p*4]) ,
.extintsrc_req_config(extintsrc_req_gw[i+p*4])
);
end
end
for (i=0; i<pt.PIC_TOTAL_INT_PLUS1 ; i++) begin : SETREG for (i=0; i<pt.PIC_TOTAL_INT_PLUS1 ; i++) begin : SETREG
if (i > 0 ) begin : NON_ZERO_INT if (i > 0 ) begin : NON_ZERO_INT
@ -227,9 +270,11 @@ for (i=0; i<pt.PIC_TOTAL_INT_PLUS1 ; i++) begin : SETREG
rvdffs #(INTPRIORITY_BITS) intpriority_ff (.*, .en( intpriority_reg_we[i]), .din (picm_wr_data_ff[INTPRIORITY_BITS-1:0]), .dout(intpriority_reg[i]), .clk(pic_pri_c1_clk)); rvdffs #(INTPRIORITY_BITS) intpriority_ff (.*, .en( intpriority_reg_we[i]), .din (picm_wr_data_ff[INTPRIORITY_BITS-1:0]), .dout(intpriority_reg[i]), .clk(pic_pri_c1_clk));
rvdffs #(1) intenable_ff (.*, .en( intenable_reg_we[i]), .din (picm_wr_data_ff[0]), .dout(intenable_reg[i]), .clk(pic_int_c1_clk)); rvdffs #(1) intenable_ff (.*, .en( intenable_reg_we[i]), .din (picm_wr_data_ff[0]), .dout(intenable_reg[i]), .clk(pic_int_c1_clk));
rvdffs #(2) gw_config_ff (.*, .en( gw_config_reg_we[i]), .din (picm_wr_data_ff[1:0]), .dout(gw_config_reg[i]), .clk(gw_config_c1_clk));
assign intenable_clk_enable[i] = gw_config_reg[i][1] | intenable_reg_we[i] | intenable_reg[i] | gw_clear_reg_we[i] ; assign intenable_clk_enable[i] = gw_config_reg[i][1] | intenable_reg_we[i] | intenable_reg[i] | gw_clear_reg_we[i] ;
/*
rvsyncss_fpga #(1) sync_inst rvsyncss_fpga #(1) sync_inst
( (
.gw_clk (gw_clk[i/4]), .gw_clk (gw_clk[i/4]),
@ -241,9 +286,7 @@ for (i=0; i<pt.PIC_TOTAL_INT_PLUS1 ; i++) begin : SETREG
// if (GW_CONFIG[i]) begin
rvdffs #(2) gw_config_ff (.*, .en( gw_config_reg_we[i]), .din (picm_wr_data_ff[1:0]), .dout(gw_config_reg[i]), .clk(gw_config_c1_clk));
el2_configurable_gw config_gw_inst(.*, el2_configurable_gw config_gw_inst(.*,
.gw_clk(gw_clk[i/4]), .gw_clk(gw_clk[i/4]),
@ -255,6 +298,7 @@ for (i=0; i<pt.PIC_TOTAL_INT_PLUS1 ; i++) begin : SETREG
.meigwclr(gw_clear_reg_we[i]) , .meigwclr(gw_clear_reg_we[i]) ,
.extintsrc_req_config(extintsrc_req_gw[i]) .extintsrc_req_config(extintsrc_req_gw[i])
); );
*/
end else begin : INT_ZERO end else begin : INT_ZERO
assign intpriority_reg_we[i] = 1'b0 ; assign intpriority_reg_we[i] = 1'b0 ;
@ -285,6 +329,10 @@ end
assign pl_in[INTPRIORITY_BITS-1:0] = selected_int_priority[INTPRIORITY_BITS-1:0] ; assign pl_in[INTPRIORITY_BITS-1:0] = selected_int_priority[INTPRIORITY_BITS-1:0] ;
//if (pt.PIC_2CYCLE == 1) begin : genblock
//end
//else begin : genblock
//end
genvar l, m , j, k; genvar l, m , j, k;
@ -512,7 +560,7 @@ module el2_configurable_gw (
input logic rawclk, input logic rawclk,
input logic clken, input logic clken,
input logic rst_l, input logic rst_l,
input logic extintsrc_req_sync , input logic extintsrc_req ,
input logic meigwctrl_polarity , input logic meigwctrl_polarity ,
input logic meigwctrl_type , input logic meigwctrl_type ,
input logic meigwclr , input logic meigwclr ,
@ -521,7 +569,13 @@ module el2_configurable_gw (
); );
logic gw_int_pending_in , gw_int_pending ; logic gw_int_pending_in, gw_int_pending, extintsrc_req_sync;
rvsyncss_fpga #(1) sync_inst (
.dout (extintsrc_req_sync),
.din (extintsrc_req),
.*) ;
assign gw_int_pending_in = (extintsrc_req_sync ^ meigwctrl_polarity) | (gw_int_pending & ~meigwclr) ; assign gw_int_pending_in = (extintsrc_req_sync ^ meigwctrl_polarity) | (gw_int_pending & ~meigwclr) ;
rvdff_fpga #(1) int_pend_ff (.*, .clk(gw_clk), .rawclk(rawclk), .clken(clken), .din (gw_int_pending_in), .dout(gw_int_pending)); rvdff_fpga #(1) int_pend_ff (.*, .clk(gw_clk), .rawclk(rawclk), .clken(clken), .din (gw_int_pending_in), .dout(gw_int_pending));

129
design/exu/el2_exu_alu_ctl.sv
View File

@ -75,31 +75,27 @@ import el2_pkg::*;
// Zbb // Zbb
logic ap_clz; logic ap_clz;
logic ap_ctz; logic ap_ctz;
logic ap_pcnt; logic ap_cpop;
logic ap_sext_b; logic ap_sext_b;
logic ap_sext_h; logic ap_sext_h;
logic ap_min; logic ap_min;
logic ap_max; logic ap_max;
logic ap_pack;
logic ap_packu;
logic ap_packh;
logic ap_rol; logic ap_rol;
logic ap_ror; logic ap_ror;
logic ap_rev;
logic ap_rev8; logic ap_rev8;
logic ap_orc_b; logic ap_orc_b;
logic ap_orc16;
logic ap_zbb; logic ap_zbb;
// Zbs // Zbs
logic ap_sbset; logic ap_bset;
logic ap_sbclr; logic ap_bclr;
logic ap_sbinv; logic ap_binv;
logic ap_sbext; logic ap_bext;
// Zbr // Zbp
logic ap_slo; logic ap_pack;
logic ap_sro; logic ap_packu;
logic ap_packh;
// Zba // Zba
logic ap_sh1add; logic ap_sh1add;
@ -113,7 +109,7 @@ import el2_pkg::*;
begin begin
assign ap_clz = ap.clz; assign ap_clz = ap.clz;
assign ap_ctz = ap.ctz; assign ap_ctz = ap.ctz;
assign ap_pcnt = ap.pcnt; assign ap_cpop = ap.cpop;
assign ap_sext_b = ap.sext_b; assign ap_sext_b = ap.sext_b;
assign ap_sext_h = ap.sext_h; assign ap_sext_h = ap.sext_h;
assign ap_min = ap.min; assign ap_min = ap.min;
@ -123,7 +119,7 @@ import el2_pkg::*;
begin begin
assign ap_clz = 1'b0; assign ap_clz = 1'b0;
assign ap_ctz = 1'b0; assign ap_ctz = 1'b0;
assign ap_pcnt = 1'b0; assign ap_cpop = 1'b0;
assign ap_sext_b = 1'b0; assign ap_sext_b = 1'b0;
assign ap_sext_h = 1'b0; assign ap_sext_h = 1'b0;
assign ap_min = 1'b0; assign ap_min = 1'b0;
@ -133,57 +129,57 @@ import el2_pkg::*;
if ( (pt.BITMANIP_ZBB == 1) | (pt.BITMANIP_ZBP == 1) ) if ( (pt.BITMANIP_ZBB == 1) | (pt.BITMANIP_ZBP == 1) )
begin begin
assign ap_pack = ap.pack;
assign ap_packu = ap.packu;
assign ap_packh = ap.packh;
assign ap_rol = ap.rol; assign ap_rol = ap.rol;
assign ap_ror = ap.ror; assign ap_ror = ap.ror;
assign ap_rev = ap.grev & (b_in[4:0] == 5'b11111);
assign ap_rev8 = ap.grev & (b_in[4:0] == 5'b11000); assign ap_rev8 = ap.grev & (b_in[4:0] == 5'b11000);
assign ap_orc_b = ap.gorc & (b_in[4:0] == 5'b00111); assign ap_orc_b = ap.gorc & (b_in[4:0] == 5'b00111);
assign ap_orc16 = ap.gorc & (b_in[4:0] == 5'b10000);
assign ap_zbb = ap.zbb; assign ap_zbb = ap.zbb;
end end
else else
begin begin
assign ap_pack = 1'b0;
assign ap_packu = 1'b0;
assign ap_packh = 1'b0;
assign ap_rol = 1'b0; assign ap_rol = 1'b0;
assign ap_ror = 1'b0; assign ap_ror = 1'b0;
assign ap_rev = 1'b0;
assign ap_rev8 = 1'b0; assign ap_rev8 = 1'b0;
assign ap_orc_b = 1'b0; assign ap_orc_b = 1'b0;
assign ap_orc16 = 1'b0;
assign ap_zbb = 1'b0; assign ap_zbb = 1'b0;
end end
if (pt.BITMANIP_ZBS == 1) if (pt.BITMANIP_ZBS == 1)
begin begin
assign ap_sbset = ap.sbset; assign ap_bset = ap.bset;
assign ap_sbclr = ap.sbclr; assign ap_bclr = ap.bclr;
assign ap_sbinv = ap.sbinv; assign ap_binv = ap.binv;
assign ap_sbext = ap.sbext; assign ap_bext = ap.bext;
end end
else else
begin begin
assign ap_sbset = 1'b0; assign ap_bset = 1'b0;
assign ap_sbclr = 1'b0; assign ap_bclr = 1'b0;
assign ap_sbinv = 1'b0; assign ap_binv = 1'b0;
assign ap_sbext = 1'b0; assign ap_bext = 1'b0;
end end
if (pt.BITMANIP_ZBP == 1) if (pt.BITMANIP_ZBP == 1)
begin begin
assign ap_slo = ap.slo; assign ap_packu = ap.packu;
assign ap_sro = ap.sro;
end end
else else
begin begin
assign ap_slo = 1'b0; assign ap_packu = 1'b0;
assign ap_sro = 1'b0; end
if ( (pt.BITMANIP_ZBB == 1) | (pt.BITMANIP_ZBP == 1) | (pt.BITMANIP_ZBE == 1) | (pt.BITMANIP_ZBF == 1) )
begin
assign ap_pack = ap.pack;
assign ap_packh = ap.packh;
end
else
begin
assign ap_pack = 1'b0;
assign ap_packh = 1'b0;
end end
@ -278,7 +274,6 @@ import el2_pkg::*;
// * * * * * * * * * * * * * * * * * * BitManip : SLO,SRO * * * * * * * * * * * * * * * * * *
// * * * * * * * * * * * * * * * * * * BitManip : ROL,ROR * * * * * * * * * * * * * * * * * * // * * * * * * * * * * * * * * * * * * BitManip : ROL,ROR * * * * * * * * * * * * * * * * * *
// * * * * * * * * * * * * * * * * * * BitManip : ZBEXT * * * * * * * * * * * * * * * * * * // * * * * * * * * * * * * * * * * * * BitManip : ZBEXT * * * * * * * * * * * * * * * * * *
@ -293,12 +288,10 @@ import el2_pkg::*;
( { 6{ap.sra}} & {1'b0,b_in[4:0]} ) | ( { 6{ap.sra}} & {1'b0,b_in[4:0]} ) |
( { 6{ap_rol}} & (6'd32 - {1'b0,b_in[4:0]}) ) | ( { 6{ap_rol}} & (6'd32 - {1'b0,b_in[4:0]}) ) |
( { 6{ap_ror}} & {1'b0,b_in[4:0]} ) | ( { 6{ap_ror}} & {1'b0,b_in[4:0]} ) |
( { 6{ap_slo}} & (6'd32 - {1'b0,b_in[4:0]}) ) | ( { 6{ap_bext}} & {1'b0,b_in[4:0]} );
( { 6{ap_sro}} & {1'b0,b_in[4:0]} ) |
( { 6{ap_sbext}} & {1'b0,b_in[4:0]} );
assign shift_mask[31:0] = ( 32'hffffffff << ({5{ap.sll | ap_slo}} & b_in[4:0]) ); assign shift_mask[31:0] = ( 32'hffffffff << ({5{ap.sll}} & b_in[4:0]) );
assign shift_extend[31:0] = a_in[31:0]; assign shift_extend[31:0] = a_in[31:0];
@ -306,14 +299,12 @@ import el2_pkg::*;
assign shift_extend[62:32] = ( {31{ap.sra}} & {31{a_in[31]}} ) | assign shift_extend[62:32] = ( {31{ap.sra}} & {31{a_in[31]}} ) |
( {31{ap.sll}} & a_in[30:0] ) | ( {31{ap.sll}} & a_in[30:0] ) |
( {31{ap_rol}} & a_in[30:0] ) | ( {31{ap_rol}} & a_in[30:0] ) |
( {31{ap_ror}} & a_in[30:0] ) | ( {31{ap_ror}} & a_in[30:0] );
( {31{ap_slo}} & a_in[30:0] ) |
( {31{ap_sro}} & {31{ 1'b1 }} );
assign shift_long[62:0] = ( shift_extend[62:0] >> shift_amount[4:0] ); // 62-32 unused assign shift_long[62:0] = ( shift_extend[62:0] >> shift_amount[4:0] ); // 62-32 unused
assign sout[31:0] = ( shift_long[31:0] & shift_mask[31:0] ) | ( {32{ap_slo}} & ~shift_mask[31:0] ); assign sout[31:0] = shift_long[31:0] & shift_mask[31:0];
@ -363,26 +354,26 @@ import el2_pkg::*;
// * * * * * * * * * * * * * * * * * * BitManip : PCNT * * * * * * * * * * * * * * * * * * // * * * * * * * * * * * * * * * * * * BitManip : CPOP * * * * * * * * * * * * * * * * * *
logic [5:0] bitmanip_pcnt; logic [5:0] bitmanip_cpop;
logic [5:0] bitmanip_pcnt_result; logic [5:0] bitmanip_cpop_result;
integer bitmanip_pcnt_i; integer bitmanip_cpop_i;
always_comb always_comb
begin begin
bitmanip_pcnt[5:0] = 6'b0; bitmanip_cpop[5:0] = 6'b0;
for (bitmanip_pcnt_i=0; bitmanip_pcnt_i<32; bitmanip_pcnt_i++) for (bitmanip_cpop_i=0; bitmanip_cpop_i<32; bitmanip_cpop_i++)
begin begin
bitmanip_pcnt[5:0] = bitmanip_pcnt[5:0] + {5'b0,a_in[bitmanip_pcnt_i]}; bitmanip_cpop[5:0] = bitmanip_cpop[5:0] + {5'b0,a_in[bitmanip_cpop_i]};
end // FOR bitmanip_pcnt_i end // FOR bitmanip_cpop_i
end // ALWAYS_COMB end // ALWAYS_COMB
assign bitmanip_pcnt_result[5:0] = {6{ap_pcnt}} & bitmanip_pcnt[5:0]; assign bitmanip_cpop_result[5:0] = {6{ap_cpop}} & bitmanip_cpop[5:0];
@ -404,7 +395,6 @@ import el2_pkg::*;
assign bitmanip_minmax_sel = ap_min | ap_max; assign bitmanip_minmax_sel = ap_min | ap_max;
logic bitmanip_minmax_sel_a; logic bitmanip_minmax_sel_a;
assign bitmanip_minmax_sel_a = ge ^ ap_min; assign bitmanip_minmax_sel_a = ge ^ ap_min;
@ -414,6 +404,7 @@ import el2_pkg::*;
// * * * * * * * * * * * * * * * * * * BitManip : PACK, PACKU, PACKH * * * * * * * * * * * * * * * // * * * * * * * * * * * * * * * * * * BitManip : PACK, PACKU, PACKH * * * * * * * * * * * * * * *
logic [31:0] bitmanip_pack_result; logic [31:0] bitmanip_pack_result;
@ -426,18 +417,10 @@ import el2_pkg::*;
// * * * * * * * * * * * * * * * * * * BitManip : REV, REV8, ORC_B * * * * * * * * * * * * * * * * // * * * * * * * * * * * * * * * * * * BitManip : REV, ORC_B * * * * * * * * * * * * * * * * * *
logic [31:0] bitmanip_rev_result;
logic [31:0] bitmanip_rev8_result; logic [31:0] bitmanip_rev8_result;
logic [31:0] bitmanip_orc_b_result; logic [31:0] bitmanip_orc_b_result;
logic [31:0] bitmanip_orc16_result;
assign bitmanip_rev_result[31:0] = {32{ap_rev}} &
{a_in[00],a_in[01],a_in[02],a_in[03],a_in[04],a_in[05],a_in[06],a_in[07],
a_in[08],a_in[09],a_in[10],a_in[11],a_in[12],a_in[13],a_in[14],a_in[15],
a_in[16],a_in[17],a_in[18],a_in[19],a_in[20],a_in[21],a_in[22],a_in[23],
a_in[24],a_in[25],a_in[26],a_in[27],a_in[28],a_in[29],a_in[30],a_in[31]};
assign bitmanip_rev8_result[31:0] = {32{ap_rev8}} & {a_in[7:0],a_in[15:8],a_in[23:16],a_in[31:24]}; assign bitmanip_rev8_result[31:0] = {32{ap_rev8}} & {a_in[7:0],a_in[15:8],a_in[23:16],a_in[31:24]};
@ -466,8 +449,6 @@ import el2_pkg::*;
assign bitmanip_orc_b_result[31:0] = {32{ap_orc_b}} & { {8{| a_in[31:24]}}, {8{| a_in[23:16]}}, {8{| a_in[15:8]}}, {8{| a_in[7:0]}} }; assign bitmanip_orc_b_result[31:0] = {32{ap_orc_b}} & { {8{| a_in[31:24]}}, {8{| a_in[23:16]}}, {8{| a_in[15:8]}}, {8{| a_in[7:0]}} };
assign bitmanip_orc16_result[31:0] = {32{ap_orc16}} & { {a_in[31:16] | a_in[15:0]}, {a_in[31:16] | a_in[15:0]} };
// * * * * * * * * * * * * * * * * * * BitManip : ZBSET, ZBCLR, ZBINV * * * * * * * * * * * * * * // * * * * * * * * * * * * * * * * * * BitManip : ZBSET, ZBCLR, ZBINV * * * * * * * * * * * * * *
@ -477,16 +458,16 @@ import el2_pkg::*;
assign bitmanip_sb_1hot[31:0] = ( 32'h00000001 << b_in[4:0] ); assign bitmanip_sb_1hot[31:0] = ( 32'h00000001 << b_in[4:0] );
assign bitmanip_sb_data[31:0] = ( {32{ap_sbset}} & ( a_in[31:0] | bitmanip_sb_1hot[31:0]) ) | assign bitmanip_sb_data[31:0] = ( {32{ap_bset}} & ( a_in[31:0] | bitmanip_sb_1hot[31:0]) ) |
( {32{ap_sbclr}} & ( a_in[31:0] & ~bitmanip_sb_1hot[31:0]) ) | ( {32{ap_bclr}} & ( a_in[31:0] & ~bitmanip_sb_1hot[31:0]) ) |
( {32{ap_sbinv}} & ( a_in[31:0] ^ bitmanip_sb_1hot[31:0]) ); ( {32{ap_binv}} & ( a_in[31:0] ^ bitmanip_sb_1hot[31:0]) );
assign sel_shift = ap.sll | ap.srl | ap.sra | ap_slo | ap_sro | ap_rol | ap_ror; assign sel_shift = ap.sll | ap.srl | ap.sra | ap_rol | ap_ror;
assign sel_adder = (ap.add | ap.sub | ap_zba) & ~ap.slt & ~ap_min & ~ap_max; assign sel_adder = (ap.add | ap.sub | ap_zba) & ~ap.slt & ~ap_min & ~ap_max;
assign sel_pc = ap.jal | pp_in.pcall | pp_in.pja | pp_in.pret; assign sel_pc = ap.jal | pp_in.pcall | pp_in.pja | pp_in.pret;
assign csr_write_data[31:0]= (ap.csr_imm) ? b_in[31:0] : a_in[31:0]; assign csr_write_data[31:0]= (ap.csr_imm) ? b_in[31:0] : a_in[31:0];
@ -501,18 +482,16 @@ import el2_pkg::*;
({32{sel_pc}} & {pcout[31:1],1'b0} ) | ({32{sel_pc}} & {pcout[31:1],1'b0} ) |
({32{ap.csr_write}} & csr_write_data[31:0] ) | ({32{ap.csr_write}} & csr_write_data[31:0] ) |
{31'b0, slt_one} | {31'b0, slt_one} |
({32{ap_sbext}} & {31'b0, sout[0]} ) | ({32{ap_bext}} & {31'b0, sout[0]} ) |
{26'b0, bitmanip_clz_ctz_result[5:0]} | {26'b0, bitmanip_clz_ctz_result[5:0]} |
{26'b0, bitmanip_pcnt_result[5:0]} | {26'b0, bitmanip_cpop_result[5:0]} |
bitmanip_sext_result[31:0] | bitmanip_sext_result[31:0] |
bitmanip_minmax_result[31:0] | bitmanip_minmax_result[31:0] |
bitmanip_pack_result[31:0] | bitmanip_pack_result[31:0] |
bitmanip_packu_result[31:0] | bitmanip_packu_result[31:0] |
bitmanip_packh_result[31:0] | bitmanip_packh_result[31:0] |
bitmanip_rev_result[31:0] |
bitmanip_rev8_result[31:0] | bitmanip_rev8_result[31:0] |
bitmanip_orc_b_result[31:0] | bitmanip_orc_b_result[31:0] |
bitmanip_orc16_result[31:0] |
bitmanip_sb_data[31:0]; bitmanip_sb_data[31:0];

200
design/exu/el2_exu_mul_ctl.sv
View File

@ -53,8 +53,8 @@ import el2_pkg::*;
// ZBE // ZBE
logic ap_bext; logic ap_bcompress;
logic ap_bdep; logic ap_bdecompress;
// ZBC // ZBC
logic ap_clmul; logic ap_clmul;
@ -66,6 +66,9 @@ import el2_pkg::*;
logic ap_gorc; logic ap_gorc;
logic ap_shfl; logic ap_shfl;
logic ap_unshfl; logic ap_unshfl;
logic ap_xperm_n;
logic ap_xperm_b;
logic ap_xperm_h;
// ZBR // ZBR
logic ap_crc32_b; logic ap_crc32_b;
@ -81,13 +84,13 @@ import el2_pkg::*;
if (pt.BITMANIP_ZBE == 1) if (pt.BITMANIP_ZBE == 1)
begin begin
assign ap_bext = mul_p.bext; assign ap_bcompress = mul_p.bcompress;
assign ap_bdep = mul_p.bdep; assign ap_bdecompress = mul_p.bdecompress;
end end
else else
begin begin
assign ap_bext = 1'b0; assign ap_bcompress = 1'b0;
assign ap_bdep = 1'b0; assign ap_bdecompress = 1'b0;
end end
if (pt.BITMANIP_ZBC == 1) if (pt.BITMANIP_ZBC == 1)
@ -109,6 +112,9 @@ import el2_pkg::*;
assign ap_gorc = mul_p.gorc; assign ap_gorc = mul_p.gorc;
assign ap_shfl = mul_p.shfl; assign ap_shfl = mul_p.shfl;
assign ap_unshfl = mul_p.unshfl; assign ap_unshfl = mul_p.unshfl;
assign ap_xperm_n = mul_p.xperm_n;
assign ap_xperm_b = mul_p.xperm_b;
assign ap_xperm_h = mul_p.xperm_h;
end end
else else
begin begin
@ -116,6 +122,9 @@ import el2_pkg::*;
assign ap_gorc = 1'b0; assign ap_gorc = 1'b0;
assign ap_shfl = 1'b0; assign ap_shfl = 1'b0;
assign ap_unshfl = 1'b0; assign ap_unshfl = 1'b0;
assign ap_xperm_n = 1'b0;
assign ap_xperm_b = 1'b0;
assign ap_xperm_h = 1'b0;
end end
if (pt.BITMANIP_ZBR == 1) if (pt.BITMANIP_ZBR == 1)
@ -175,59 +184,61 @@ import el2_pkg::*;
assign prod_x[65:0] = rs1_x * rs2_x; assign prod_x[65:0] = rs1_x * rs2_x;
// * * * * * * * * * * * * * * * * * * BitManip : BEXT, BDEP * * * * * * * * * * * * * * * * * *
// *** BEXT == "gather" *** // * * * * * * * * * * * * * * * * * * BitManip : BCOMPRESS, BDECOMPRESS * * * * * * * * * * * * *
logic [31:0] bext_d;
logic bext_test_bit_d; // *** BCOMPRESS == "gather" ***
integer bext_i, bext_j;
logic [31:0] bcompress_d;
logic bcompress_test_bit_d;
integer bcompress_i, bcompress_j;
always_comb always_comb
begin begin
bext_j = 0; bcompress_j = 0;
bext_test_bit_d = 1'b0; bcompress_test_bit_d = 1'b0;
bext_d[31:0] = 32'b0; bcompress_d[31:0] = 32'b0;
for (bext_i=0; bext_i<32; bext_i++) for (bcompress_i=0; bcompress_i<32; bcompress_i++)
begin begin
bext_test_bit_d = rs2_in[bext_i]; bcompress_test_bit_d = rs2_in[bcompress_i];
if (bext_test_bit_d) if (bcompress_test_bit_d)
begin begin
bext_d[bext_j] = rs1_in[bext_i]; bcompress_d[bcompress_j] = rs1_in[bcompress_i];
bext_j = bext_j + 1; bcompress_j = bcompress_j + 1;
end // IF bext_test_bit end // IF bcompress_test_bit
end // FOR bext_i end // FOR bcompress_i
end // ALWAYS_COMB end // ALWAYS_COMB
// *** BDEP == "scatter" *** // *** BDECOMPRESS == "scatter" ***
logic [31:0] bdep_d; logic [31:0] bdecompress_d;
logic bdep_test_bit_d; logic bdecompress_test_bit_d;
integer bdep_i, bdep_j; integer bdecompress_i, bdecompress_j;
always_comb always_comb
begin begin
bdep_j = 0; bdecompress_j = 0;
bdep_test_bit_d = 1'b0; bdecompress_test_bit_d = 1'b0;
bdep_d[31:0] = 32'b0; bdecompress_d[31:0] = 32'b0;
for (bdep_i=0; bdep_i<32; bdep_i++) for (bdecompress_i=0; bdecompress_i<32; bdecompress_i++)
begin begin
bdep_test_bit_d = rs2_in[bdep_i]; bdecompress_test_bit_d = rs2_in[bdecompress_i];
if (bdep_test_bit_d) if (bdecompress_test_bit_d)
begin begin
bdep_d[bdep_i] = rs1_in[bdep_j]; bdecompress_d[bdecompress_i] = rs1_in[bdecompress_j];
bdep_j = bdep_j + 1; bdecompress_j = bdecompress_j + 1;
end // IF bdep_test_bit end // IF bdecompress_test_bit
end // FOR bdep_i end // FOR bdecompress_i
end // ALWAYS_COMB end // ALWAYS_COMB
@ -450,6 +461,88 @@ import el2_pkg::*;
// * * * * * * * * * * * * * * * * * * BitManip : XPERM * * * * * * * * * * * * * * * * *
//
// These instructions operate on nibbles/bytes/half-words/words.
// rs1 is a vector of data words and rs2 is a vector of indices into rs1.
// The result of the instruction is the vector rs2 with each element replaced by the corresponding data word from rs1,
// or zero then the index in rs2 is out of bounds.
//
// uint_xlen_t xperm(uint_xlen_t rs1, uint_xlen_t rs2, int sz_log2)
// {
// uint_xlen_t r = 0;
// uint_xlen_t sz = 1LL << sz_log2;
// uint_xlen_t mask = (1LL << sz) - 1;
// for (int i = 0; i < XLEN; i += sz)
// { uint_xlen_t pos = ((rs2 >> i) & mask) << sz_log2;
// if (pos < XLEN)
// r |= ((rs1 >> pos) & mask) << i;
// }
// return r;
// }
//
// uint_xlen_t xperm_n (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 2); }
// uint_xlen_t xperm_b (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 3); }
// uint_xlen_t xperm_h (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 4); }
// uint_xlen_t xperm_w (uint_xlen_t rs1, uint_xlen_t rs2) { return xperm(rs1, rs2, 5); } Not part of RV32
//
// The xperm.[nbhw] instructions can be implemented with an XLEN/4-lane nibble-wide crossbarswitch.
// *** XPERM_B ***
// XLEN = 32
// SZ_LOG2 = 3
// SZ = 4'd8;
// MASK = ( 1 << 8 ) - 1
// = 8'hFF
// integer xperm_b_i;
// logic [31:0] xperm_b_r;
// logic [3:0] xperm_b_sz;
// logic [7:0] xperm_b_mask;
// logic [31:0] xperm_b_pos;
//
//
// assign xperm_b_sz[3:0] = 4'd8;
// assign xperm_b_mask[7:0] = 8'hff;
//
// always_comb
// begin
// xperm_b_r[31:0] = 32'b0;
//
// for (xperm_b_i=0; xperm_b_i<32; xperm_b_i = xperm_b_i + xperm_b_sz) // This code did not work...
// begin
// xperm_b_pos[31:0] = ( (rs2_in[31:0] >> xperm_b_i) & {24'h0,xperm_b_mask[7:0]} ) << 3;
// if (xperm_b_pos[31:0] < 32'd32)
// xperm_b_r[31:0] = xperm_b_r[31:0] | ( ((rs1_in[31:0] >> xperm_b_pos[4:0]) & {24'h0,xperm_b_mask[7:0]}) << xperm_b_i );
// end
// end
logic [31:0] xperm_n;
logic [31:0] xperm_b;
logic [31:0] xperm_h;
assign xperm_n[03:00] = { 4{ ~rs2_in[03] }} & ( (rs1_in[31:0] >> {rs2_in[02:00],2'b0}) & 4'hf ); // This is a 8:1 mux with qualified selects
assign xperm_n[07:04] = { 4{ ~rs2_in[07] }} & ( (rs1_in[31:0] >> {rs2_in[06:04],2'b0}) & 4'hf );
assign xperm_n[11:08] = { 4{ ~rs2_in[11] }} & ( (rs1_in[31:0] >> {rs2_in[10:08],2'b0}) & 4'hf );
assign xperm_n[15:12] = { 4{ ~rs2_in[15] }} & ( (rs1_in[31:0] >> {rs2_in[14:12],2'b0}) & 4'hf );
assign xperm_n[19:16] = { 4{ ~rs2_in[19] }} & ( (rs1_in[31:0] >> {rs2_in[18:16],2'b0}) & 4'hf );
assign xperm_n[23:20] = { 4{ ~rs2_in[23] }} & ( (rs1_in[31:0] >> {rs2_in[22:20],2'b0}) & 4'hf );
assign xperm_n[27:24] = { 4{ ~rs2_in[27] }} & ( (rs1_in[31:0] >> {rs2_in[26:24],2'b0}) & 4'hf );
assign xperm_n[31:28] = { 4{ ~rs2_in[31] }} & ( (rs1_in[31:0] >> {rs2_in[30:28],2'b0}) & 4'hf );
assign xperm_b[07:00] = { 8{ ~(| rs2_in[07:02]) }} & ( (rs1_in[31:0] >> {rs2_in[01:00],3'b0}) & 8'hff ); // This is a 4:1 mux with qualified selects
assign xperm_b[15:08] = { 8{ ~(| rs2_in[15:10]) }} & ( (rs1_in[31:0] >> {rs2_in[09:08],3'b0}) & 8'hff );
assign xperm_b[23:16] = { 8{ ~(| rs2_in[23:18]) }} & ( (rs1_in[31:0] >> {rs2_in[17:16],3'b0}) & 8'hff );
assign xperm_b[31:24] = { 8{ ~(| rs2_in[31:26]) }} & ( (rs1_in[31:0] >> {rs2_in[25:24],3'b0}) & 8'hff );
assign xperm_h[15:00] = {16{ ~(| rs2_in[15:01]) }} & ( (rs1_in[31:0] >> {rs2_in[00] ,4'b0}) & 16'hffff ); // This is a 2:1 mux with qualified selects
assign xperm_h[31:16] = {16{ ~(| rs2_in[31:17]) }} & ( (rs1_in[31:0] >> {rs2_in[16] ,4'b0}) & 16'hffff );
// * * * * * * * * * * * * * * * * * * BitManip : CRC32, CRC32c * * * * * * * * * * * * * * * * * // * * * * * * * * * * * * * * * * * * BitManip : CRC32, CRC32c * * * * * * * * * * * * * * * * *
// *** computed from https: //crccalc.com *** // *** computed from https: //crccalc.com ***
@ -564,12 +657,26 @@ import el2_pkg::*;
// * * * * * * * * * * * * * * * * * * BitManip : BFP * * * * * * * * * * * * * * * * * * // * * * * * * * * * * * * * * * * * * BitManip : BFP * * * * * * * * * * * * * * * * * *
// uint_xlen_t bfp(uint_xlen_t rs1, uint_xlen_t rs2)
// {
// uint_xlen_t cfg = rs2 >> (XLEN/2);
// if ((cfg >> 30) == 2) cfg = cfg >> 16;
// int len = (cfg >> 8) & (XLEN/2-1);
// int off = cfg & (XLEN-1);
// len = len ? len : XLEN/2;
// uint_xlen_t mask = slo(0, len) << off;
// uint_xlen_t data = rs2 << off;
// return (data & mask) | (rs1 & ~mask);
logic [4:0] bfp_len; logic [4:0] bfp_len;
logic [4:0] bfp_off; logic [4:0] bfp_off;
logic [31:0] bfp_len_mask_; logic [31:0] bfp_len_mask_;
logic [31:0] bfp_off_mask_;
logic [15:0] bfp_preshift_data; logic [15:0] bfp_preshift_data;
logic [63:0] bfp_shift_data; logic [31:0] bfp_shift_data;
logic [63:0] bfp_shift_mask; logic [31:0] bfp_shift_mask;
logic [31:0] bfp_result_d; logic [31:0] bfp_result_d;
@ -578,13 +685,13 @@ import el2_pkg::*;
assign bfp_off[4:0] = rs2_in[20:16]; assign bfp_off[4:0] = rs2_in[20:16];
assign bfp_len_mask_[31:0] = 32'hffff_ffff << bfp_len[4:0]; assign bfp_len_mask_[31:0] = 32'hffff_ffff << bfp_len[4:0];
assign bfp_off_mask_[31:0] = 32'hffff_ffff << bfp_off[4:0];
assign bfp_preshift_data[15:0]= rs2_in[15:0] & ~bfp_len_mask_[15:0]; assign bfp_preshift_data[15:0]= rs2_in[15:0] & ~bfp_len_mask_[15:0];
assign bfp_shift_data[63:0] = {16'b0,bfp_preshift_data[15:0], 16'b0,bfp_preshift_data[15:0]} << bfp_off[4:0]; assign bfp_shift_data[31:0] = {16'b0,bfp_preshift_data[15:0]} << bfp_off[4:0];
assign bfp_shift_mask[63:0] = {bfp_len_mask_[31:0], bfp_len_mask_[31:0]} << bfp_off[4:0]; assign bfp_shift_mask[31:0] = (bfp_len_mask_[31:0] << bfp_off[4:0]) | ~bfp_off_mask_[31:0];
assign bfp_result_d[31:0] = bfp_shift_data[63:32] | (rs1_in[31:0] & bfp_shift_mask[63:32]);
assign bfp_result_d[31:0] = bfp_shift_data[31:0] | (rs1_in[31:0] & bfp_shift_mask[31:0]);
@ -592,10 +699,10 @@ import el2_pkg::*;
// * * * * * * * * * * * * * * * * * * BitManip : Common logic * * * * * * * * * * * * * * * * * * // * * * * * * * * * * * * * * * * * * BitManip : Common logic * * * * * * * * * * * * * * * * * *
assign bitmanip_sel_d = ap_bext | ap_bdep | ap_clmul | ap_clmulh | ap_clmulr | ap_grev | ap_gorc | ap_shfl | ap_unshfl | crc32_all | ap_bfp; assign bitmanip_sel_d = ap_bcompress | ap_bdecompress | ap_clmul | ap_clmulh | ap_clmulr | ap_grev | ap_gorc | ap_shfl | ap_unshfl | crc32_all | ap_bfp | ap_xperm_n | ap_xperm_b | ap_xperm_h;
assign bitmanip_d[31:0] = ( {32{ap_bext}} & bext_d[31:0] ) | assign bitmanip_d[31:0] = ( {32{ap_bcompress}} & bcompress_d[31:0] ) |
( {32{ap_bdep}} & bdep_d[31:0] ) | ( {32{ap_bdecompress}} & bdecompress_d[31:0] ) |
( {32{ap_clmul}} & clmul_raw_d[31:0] ) | ( {32{ap_clmul}} & clmul_raw_d[31:0] ) |
( {32{ap_clmulh}} & {1'b0,clmul_raw_d[62:32]} ) | ( {32{ap_clmulh}} & {1'b0,clmul_raw_d[62:32]} ) |
( {32{ap_clmulr}} & clmul_raw_d[62:31] ) | ( {32{ap_clmulr}} & clmul_raw_d[62:31] ) |
@ -609,7 +716,10 @@ import el2_pkg::*;
( {32{ap_crc32c_b}} & crc32c_bd[31:0] ) | ( {32{ap_crc32c_b}} & crc32c_bd[31:0] ) |
( {32{ap_crc32c_h}} & crc32c_hd[31:0] ) | ( {32{ap_crc32c_h}} & crc32c_hd[31:0] ) |
( {32{ap_crc32c_w}} & crc32c_wd[31:0] ) | ( {32{ap_crc32c_w}} & crc32c_wd[31:0] ) |
( {32{ap_bfp}} & bfp_result_d[31:0] ); ( {32{ap_bfp}} & bfp_result_d[31:0] ) |
( {32{ap_xperm_n}} & xperm_n[31:0] ) |
( {32{ap_xperm_b}} & xperm_b[31:0] ) |
( {32{ap_xperm_h}} & xperm_h[31:0] );

43
design/flist Normal file
View File

@ -0,0 +1,43 @@
$RV_ROOT/design/el2_swerv_wrapper.sv
$RV_ROOT/design/el2_mem.sv
$RV_ROOT/design/el2_pic_ctrl.sv
$RV_ROOT/design/el2_swerv.sv
$RV_ROOT/design/el2_dma_ctrl.sv
$RV_ROOT/design/ifu/el2_ifu_aln_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_compress_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_ifc_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_bp_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_ic_mem.sv
$RV_ROOT/design/ifu/el2_ifu_mem_ctl.sv
$RV_ROOT/design/ifu/el2_ifu_iccm_mem.sv
$RV_ROOT/design/ifu/el2_ifu.sv
$RV_ROOT/design/dec/el2_dec_decode_ctl.sv
$RV_ROOT/design/dec/el2_dec_gpr_ctl.sv
$RV_ROOT/design/dec/el2_dec_ib_ctl.sv
$RV_ROOT/design/dec/el2_dec_tlu_ctl.sv
$RV_ROOT/design/dec/el2_dec_trigger.sv
$RV_ROOT/design/dec/el2_dec.sv
$RV_ROOT/design/exu/el2_exu_alu_ctl.sv
$RV_ROOT/design/exu/el2_exu_mul_ctl.sv
$RV_ROOT/design/exu/el2_exu_div_ctl.sv
$RV_ROOT/design/exu/el2_exu.sv
$RV_ROOT/design/lsu/el2_lsu.sv
$RV_ROOT/design/lsu/el2_lsu_clkdomain.sv
$RV_ROOT/design/lsu/el2_lsu_addrcheck.sv
$RV_ROOT/design/lsu/el2_lsu_lsc_ctl.sv
$RV_ROOT/design/lsu/el2_lsu_stbuf.sv
$RV_ROOT/design/lsu/el2_lsu_bus_buffer.sv
$RV_ROOT/design/lsu/el2_lsu_bus_intf.sv
$RV_ROOT/design/lsu/el2_lsu_ecc.sv
$RV_ROOT/design/lsu/el2_lsu_dccm_mem.sv
$RV_ROOT/design/lsu/el2_lsu_dccm_ctl.sv
$RV_ROOT/design/lsu/el2_lsu_trigger.sv
$RV_ROOT/design/dbg/el2_dbg.sv
$RV_ROOT/design/dmi/dmi_wrapper.v
$RV_ROOT/design/dmi/dmi_jtag_to_core_sync.v
$RV_ROOT/design/dmi/rvjtag_tap.v
$RV_ROOT/design/lib/el2_lib.sv
-v $RV_ROOT/design/lib/beh_lib.sv
-v $RV_ROOT/design/lib/mem_lib.sv
$RV_ROOT/design/lib/ahb_to_axi4.sv
$RV_ROOT/design/lib/axi4_to_ahb.sv

9
design/ifu/el2_ifu_aln_ctl.sv
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@ -186,8 +186,8 @@ import el2_pkg::*;
logic consume_fb1, consume_fb0; logic consume_fb1, consume_fb0;
logic [1:0] icaf_eff; logic [1:0] icaf_eff;
localparam BRDATA_SIZE = pt.BTB_ENABLE ? 16+($clog2(pt.BTB_SIZE)*2*pt.BTB_FULLYA) : 2; localparam BRDATA_SIZE = pt.BTB_ENABLE ? 16+($clog2(pt.BTB_SIZE)*2*pt.BTB_FULLYA) : 4;
localparam BRDATA_WIDTH = pt.BTB_ENABLE ? 8+($clog2(pt.BTB_SIZE)*pt.BTB_FULLYA) : 1; localparam BRDATA_WIDTH = pt.BTB_ENABLE ? 8+($clog2(pt.BTB_SIZE)*pt.BTB_FULLYA) : 2;
logic [BRDATA_SIZE-1:0] brdata_in, brdata2, brdata1, brdata0; logic [BRDATA_SIZE-1:0] brdata_in, brdata2, brdata1, brdata0;
logic [BRDATA_SIZE-1:0] brdata1eff, brdata0eff; logic [BRDATA_SIZE-1:0] brdata1eff, brdata0eff;
logic [BRDATA_SIZE-1:0] brdata1final, brdata0final; logic [BRDATA_SIZE-1:0] brdata1final, brdata0final;
@ -229,8 +229,9 @@ else begin
.din({qwen[2] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE-1:0]} : {misc2[MHI:0], brdata2[BRDATA_SIZE-1:0]}, .din({qwen[2] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE-1:0]} : {misc2[MHI:0], brdata2[BRDATA_SIZE-1:0]},
qwen[1] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE-1:0]} : {misc1[MHI:0], brdata1[BRDATA_SIZE-1:0]}, qwen[1] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE-1:0]} : {misc1[MHI:0], brdata1[BRDATA_SIZE-1:0]},
qwen[0] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE-1:0]} : {misc0[MHI:0], brdata0[BRDATA_SIZE-1:0]}}), qwen[0] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE-1:0]} : {misc0[MHI:0], brdata0[BRDATA_SIZE-1:0]}}),
.dout({misc2[MHI:0],misc1[MHI:0],misc0[MHI:0], .dout({misc2[MHI:0], brdata2[BRDATA_SIZE-1:0],
brdata2[BRDATA_SIZE-1:0], brdata1[BRDATA_SIZE-1:0], brdata0[BRDATA_SIZE-1:0]}) misc1[MHI:0], brdata1[BRDATA_SIZE-1:0],
misc0[MHI:0], brdata0[BRDATA_SIZE-1:0]})
); );
end end

64
design/ifu/el2_ifu_bp_ctl.sv
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@ -721,10 +721,10 @@ end // if (!pt.BTB_FULLYA)
always_comb begin always_comb begin
btb_vbank0_rd_data_f = '0; btb_vbank0_rd_data_f = '0;
btb_vbank1_rd_data_f = '0; btb_vbank1_rd_data_f = '0;
btb_tag_hit = '0; // btb_tag_hit = '0;
btb_upper_hit = '0; // btb_upper_hit = '0;
btb_offset_0 = '0; // btb_offset_0 = '0;
btb_offset_1 = '0; // btb_offset_1 = '0;
found1 = 1'b0; found1 = 1'b0;
hit0 = 1'b0; hit0 = 1'b0;
@ -734,22 +734,28 @@ end // if (!pt.BTB_FULLYA)
btb_fa_wr_addr0 = '0; btb_fa_wr_addr0 = '0;
for(int i=0; i<pt.BTB_SIZE; i++) begin for(int i=0; i<pt.BTB_SIZE; i++) begin
logic upper_hit, offset_0, offset_1;
// Break the cmp into chunks for lower area. // Break the cmp into chunks for lower area.
// Chunk1: FA 31:6 or 31:5 depending on icache line size // Chunk1: FA 31:6 or 31:5 depending on icache line size
// Chunk2: FA 5:1 or 4:1 depending on icache line size // Chunk2: FA 5:1 or 4:1 depending on icache line size
btb_upper_hit[i] = (btbdata[i][BTB_DWIDTH_TOP:FA_TAG_END_UPPER] == ifc_fetch_addr_f[31:FA_CMP_LOWER]) & btbdata[i][0] & ~wr0_en[i]; // btb_upper_hit[i] = (btbdata[i][BTB_DWIDTH_TOP:FA_TAG_END_UPPER] == ifc_fetch_addr_f[31:FA_CMP_LOWER]) & btbdata[i][0] & ~wr0_en[i];
btb_offset_0[i] = (btbdata[i][FA_TAG_START_LOWER:FA_TAG_END_LOWER] == ifc_fetch_addr_f[FA_CMP_LOWER-1:1]) & btb_upper_hit[i]; // btb_offset_0[i] = (btbdata[i][FA_TAG_START_LOWER:FA_TAG_END_LOWER] == ifc_fetch_addr_f[FA_CMP_LOWER-1:1]) & btb_upper_hit[i];
btb_offset_1[i] = (btbdata[i][FA_TAG_START_LOWER:FA_TAG_END_LOWER] == ifc_fetch_addr_p1_f[FA_CMP_LOWER-1:1]) & btb_upper_hit[i]; // btb_offset_1[i] = (btbdata[i][FA_TAG_START_LOWER:FA_TAG_END_LOWER] == ifc_fetch_addr_p1_f[FA_CMP_LOWER-1:1]) & btb_upper_hit[i];
upper_hit = (btbdata[i][BTB_DWIDTH_TOP:FA_TAG_END_UPPER] == ifc_fetch_addr_f[31:FA_CMP_LOWER]) & btbdata[i][0] & ~wr0_en[i];
offset_0 = (btbdata[i][FA_TAG_START_LOWER:FA_TAG_END_LOWER] == ifc_fetch_addr_f[FA_CMP_LOWER-1:1]) & upper_hit;
offset_1 = (btbdata[i][FA_TAG_START_LOWER:FA_TAG_END_LOWER] == ifc_fetch_addr_p1_f[FA_CMP_LOWER-1:1]) & upper_hit;
if(~hit0) begin if(~hit0) begin
if(btb_offset_0[i]) begin if(offset_0) begin
hit0_index[BTB_FA_INDEX:0] = (BTB_FA_INDEX+1)'(i); hit0_index[BTB_FA_INDEX:0] = (BTB_FA_INDEX+1)'(i);
// hit unless we are also writing this entry at the same time // hit unless we are also writing this entry at the same time
hit0 = 1'b1; hit0 = 1'b1;
end end
end end
if(~hit1) begin if(~hit1) begin
if(btb_offset_1[i]) begin if(offset_1) begin
hit1_index[BTB_FA_INDEX:0] = (BTB_FA_INDEX+1)'(i); hit1_index[BTB_FA_INDEX:0] = (BTB_FA_INDEX+1)'(i);
hit1 = 1'b1; hit1 = 1'b1;
end end
@ -757,13 +763,13 @@ end // if (!pt.BTB_FULLYA)
// Mux out the 2 potential branches // Mux out the 2 potential branches
if(btb_offset_0[i] == 1'b1) if(offset_0)
btb_vbank0_rd_data_f[BTB_DWIDTH-1:0] = fetch_mp_collision_f ? btb_wr_data : btbdata[i]; btb_vbank0_rd_data_f[BTB_DWIDTH-1:0] = fetch_mp_collision_f ? btb_wr_data : btbdata[i];
if(btb_offset_1[i] == 1'b1) if(offset_1)
btb_vbank1_rd_data_f[BTB_DWIDTH-1:0] = fetch_mp_collision_p1_f ? btb_wr_data : btbdata[i]; btb_vbank1_rd_data_f[BTB_DWIDTH-1:0] = fetch_mp_collision_p1_f ? btb_wr_data : btbdata[i];
// find the first zero from bit zero in the used vector, this is the write address // find the first zero from bit zero in the used vector, this is the write address
if(~found1) begin if(~found1 & ((exu_mp_valid_write & ~exu_mp_pkt.way) | dec_tlu_error_wb)) begin
if(~btb_used[i]) begin if(~btb_used[i]) begin
btb_fa_wr_addr0[BTB_FA_INDEX:0] = i[BTB_FA_INDEX:0]; btb_fa_wr_addr0[BTB_FA_INDEX:0] = i[BTB_FA_INDEX:0];
found1 = 1'b1; found1 = 1'b1;
@ -772,10 +778,10 @@ end // if (!pt.BTB_FULLYA)
end end
end // always_comb begin end // always_comb begin
`ifdef RV_ASSERT_ON //`ifdef RV_ASSERT_ON
btbhitonehot0: assert #0 ($onehot0(btb_offset_0)); // btbhitonehot0: assert #0 ($onehot0(btb_offset_0));
btbhitonehot1: assert #0 ($onehot0(btb_offset_1)); // btbhitonehot1: assert #0 ($onehot0(btb_offset_1));
`endif //`endif
assign vwayhit_f[1:0] = {hit1, hit0} & {eoc_mask, 1'b1}; assign vwayhit_f[1:0] = {hit1, hit0} & {eoc_mask, 1'b1};
@ -821,13 +827,16 @@ end // block: fa
// //
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0][1:0] bht_bank_wr_data ; // logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0][1:0] bht_bank_wr_data ;
logic [1:0] [pt.BHT_ARRAY_DEPTH-1:0] [1:0] bht_bank_rd_data_out ; logic [1:0] [pt.BHT_ARRAY_DEPTH-1:0] [1:0] bht_bank_rd_data_out ;
logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0] bht_bank_clken ; logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0] bht_bank_clken ;
logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0] bht_bank_clk ; logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0] bht_bank_clk ;
logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0] bht_bank_sel ; // logic [1:0] [(pt.BHT_ARRAY_DEPTH/NUM_BHT_LOOP)-1:0][NUM_BHT_LOOP-1:0] bht_bank_sel ;
for ( i=0; i<2; i++) begin : BANKS for ( i=0; i<2; i++) begin : BANKS
wire[pt.BHT_ARRAY_DEPTH-1:0] wr0, wr1;
assign wr0 = bht_wr_en0[i] << bht_wr_addr0;
assign wr1 = bht_wr_en2[i] << bht_wr_addr2;
for (genvar k=0 ; k < (pt.BHT_ARRAY_DEPTH)/NUM_BHT_LOOP ; k++) begin : BHT_CLK_GROUP for (genvar k=0 ; k < (pt.BHT_ARRAY_DEPTH)/NUM_BHT_LOOP ; k++) begin : BHT_CLK_GROUP
assign bht_bank_clken[i][k] = (bht_wr_en0[i] & ((bht_wr_addr0[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) | assign bht_bank_clken[i][k] = (bht_wr_en0[i] & ((bht_wr_addr0[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) |
(bht_wr_en2[i] & ((bht_wr_addr2[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)); (bht_wr_en2[i] & ((bht_wr_addr2[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH));
@ -836,19 +845,24 @@ end // block: fa
`endif `endif
for (j=0 ; j<NUM_BHT_LOOP ; j++) begin : BHT_FLOPS for (j=0 ; j<NUM_BHT_LOOP ; j++) begin : BHT_FLOPS
assign bht_bank_sel[i][k][j] = (bht_wr_en0[i] & (bht_wr_addr0[NUM_BHT_LOOP_INNER_HI :pt.BHT_ADDR_LO] == j) & ((bht_wr_addr0[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) | wire[1:0] wdata;
(bht_wr_en2[i] & (bht_wr_addr2[NUM_BHT_LOOP_INNER_HI :pt.BHT_ADDR_LO] == j) & ((bht_wr_addr2[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) ; wire bank_sel = wr1[NUM_BHT_LOOP*k+j] | wr0[NUM_BHT_LOOP*k+j];
// assign bht_bank_sel[i][k][j] = (bht_wr_en0[i] & (bht_wr_addr0[NUM_BHT_LOOP_INNER_HI :pt.BHT_ADDR_LO] == j) & ((bht_wr_addr0[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) |
// (bht_wr_en2[i] & (bht_wr_addr2[NUM_BHT_LOOP_INNER_HI :pt.BHT_ADDR_LO] == j) & ((bht_wr_addr2[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) ;
// assign bht_bank_wr_data[i][k][j] = (bht_wr_en2[i] & (bht_wr_addr2[NUM_BHT_LOOP_INNER_HI:pt.BHT_ADDR_LO] == j) & ((bht_wr_addr2[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) ? bht_wr_data2[1:0] :
// bht_wr_data0[1:0] ;
assign wdata = wr1[NUM_BHT_LOOP*k+j] ? bht_wr_data2[1:0] :bht_wr_data0;
assign bht_bank_wr_data[i][k][j] = (bht_wr_en2[i] & (bht_wr_addr2[NUM_BHT_LOOP_INNER_HI:pt.BHT_ADDR_LO] == j) & ((bht_wr_addr2[pt.BHT_ADDR_HI: NUM_BHT_LOOP_OUTER_LO]==k) | BHT_NO_ADDR_MATCH)) ? bht_wr_data2[1:0] :
bht_wr_data0[1:0] ;
rvdffs_fpga #(2) bht_bank (.*, rvdffs_fpga #(2) bht_bank (.*,
.clk (bht_bank_clk[i][k]), .clk (bht_bank_clk[i][k]),
.en (bht_bank_sel[i][k][j]), .en (bank_sel),
.rawclk (clk), .rawclk (clk),
.clken (bht_bank_sel[i][k][j]), .clken (bank_sel),
.din (bht_bank_wr_data[i][k][j]), .din (wdata),
.dout (bht_bank_rd_data_out[i][(16*k)+j])); .dout (bht_bank_rd_data_out[i][(16*k)+j]));
end // block: BHT_FLOPS end // block: BHT_FLOPS

2
design/ifu/el2_ifu_ic_mem.sv
View File

@ -315,7 +315,7 @@ if (pt.ICACHE_BYPASS_ENABLE == 1) begin \
end \ end \
else begin \ else begin \
assign wb_dout[i][k] = wb_dout_pre_up[i][k] ; \ assign wb_dout[i][k] = wb_dout_pre_up[i][k] ; \
assign ic_bank_way_clken_final_up[i][k] = ic_bank_way_clken[i][k]; \ assign ic_bank_way_clken_final_up[i][k] = ic_bank_way_clken[k][i]; \
end end

2
design/ifu/el2_ifu_mem_ctl.sv
View File

@ -948,7 +948,7 @@ logic perr_sb_write_status ;
case (perr_state) case (perr_state)
ERR_IDLE: begin : err_idle ERR_IDLE: begin : err_idle
perr_nxtstate = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF; perr_nxtstate = iccm_dma_sb_error ? DMA_SB_ERR : (ic_error_start & ~exu_flush_final) ? IC_WFF : ECC_WFF;
perr_state_en = (((iccm_error_start | ic_error_start) & ~exu_flush_final) | iccm_dma_sb_error) & ~dec_tlu_force_halt; perr_state_en = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt;
perr_sb_write_status = perr_state_en; perr_sb_write_status = perr_state_en;
end end
IC_WFF: begin : icache_wff // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state IC_WFF: begin : icache_wff // All the I$ data and/or Tag errors ( parity/ECC ) will come to this state

38
design/include/el2_def.sv
View File

@ -129,11 +129,9 @@ typedef struct packed {
typedef struct packed { typedef struct packed {
logic clz; logic clz;
logic ctz; logic ctz;
logic pcnt; logic cpop;
logic sext_b; logic sext_b;
logic sext_h; logic sext_h;
logic slo;
logic sro;
logic min; logic min;
logic max; logic max;
logic pack; logic pack;
@ -144,10 +142,10 @@ typedef struct packed {
logic grev; logic grev;
logic gorc; logic gorc;
logic zbb; logic zbb;
logic sbset; logic bset;
logic sbclr; logic bclr;
logic sbinv; logic binv;
logic sbext; logic bext;
logic sh1add; logic sh1add;
logic sh2add; logic sh2add;
logic sh3add; logic sh3add;
@ -205,11 +203,9 @@ typedef struct packed {
typedef struct packed { typedef struct packed {
logic clz; logic clz;
logic ctz; logic ctz;
logic pcnt; logic cpop;
logic sext_b; logic sext_b;
logic sext_h; logic sext_h;
logic slo;
logic sro;
logic min; logic min;
logic max; logic max;
logic pack; logic pack;
@ -220,13 +216,13 @@ typedef struct packed {
logic grev; logic grev;
logic gorc; logic gorc;
logic zbb; logic zbb;
logic sbset; logic bset;
logic sbclr; logic bclr;
logic sbinv; logic binv;
logic sbext;
logic zbs;
logic bext; logic bext;
logic bdep; logic zbs;
logic bcompress;
logic bdecompress;
logic zbe; logic zbe;
logic clmul; logic clmul;
logic clmulh; logic clmulh;
@ -234,6 +230,9 @@ typedef struct packed {
logic zbc; logic zbc;
logic shfl; logic shfl;
logic unshfl; logic unshfl;
logic xperm_n;
logic xperm_b;
logic xperm_h;
logic zbp; logic zbp;
logic crc32_b; logic crc32_b;
logic crc32_h; logic crc32_h;
@ -306,8 +305,8 @@ typedef struct packed {
logic rs1_sign; logic rs1_sign;
logic rs2_sign; logic rs2_sign;
logic low; logic low;
logic bext; logic bcompress;
logic bdep; logic bdecompress;
logic clmul; logic clmul;
logic clmulh; logic clmulh;
logic clmulr; logic clmulr;
@ -322,6 +321,9 @@ typedef struct packed {
logic crc32c_h; logic crc32c_h;
logic crc32c_w; logic crc32c_w;
logic bfp; logic bfp;
logic xperm_n;
logic xperm_b;
logic xperm_h;
} el2_mul_pkt_t; } el2_mul_pkt_t;
typedef struct packed { typedef struct packed {

8
design/lsu/el2_lsu_bus_intf.sv
View File

@ -211,10 +211,10 @@ import el2_pkg::*;
assign store_data_hi_r[31:0] = store_data_ext_r[63:32]; assign store_data_hi_r[31:0] = store_data_ext_r[63:32];
assign store_data_lo_r[31:0] = store_data_ext_r[31:0]; assign store_data_lo_r[31:0] = store_data_ext_r[31:0];
assign ld_addr_rhit_lo_lo = (lsu_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m; assign ld_addr_rhit_lo_lo = (lsu_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m & lsu_busreq_r;
assign ld_addr_rhit_lo_hi = (end_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m; assign ld_addr_rhit_lo_hi = (end_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m & lsu_busreq_r;
assign ld_addr_rhit_hi_lo = (lsu_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m; assign ld_addr_rhit_hi_lo = (lsu_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m & lsu_busreq_r;
assign ld_addr_rhit_hi_hi = (end_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m; assign ld_addr_rhit_hi_hi = (end_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m & lsu_busreq_r;
for (genvar i=0; i<4; i++) begin: GenBusBufFwd for (genvar i=0; i<4; i++) begin: GenBusBufFwd
assign ld_byte_rhit_lo_lo[i] = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[i] & ldst_byteen_lo_m[i]; assign ld_byte_rhit_lo_lo[i] = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[i] & ldst_byteen_lo_m[i];

23
release-notes.md
View File

@ -1,3 +1,18 @@
# EL2 SweRV RISC-V Core<sup>TM</sup> 1.4 from Western Digital
* Upgraded bit-manipulation support for Zba, Zbb, Zbc, Zbe, Zbf, Zbp, Zbr, Zbs to `0.94` draft spec.
* Zba, Zbb, Zbc and Zbs are enabled by default. Use `-set=bitmanip_zb*=1` to enable other sub-extensions.
* Simulation performance improvement coding style changes in branch predictor and PIC
* Several corner case and exotic bug fixes :
* MPC run ack timing
* Force halt mechanism and MPC
* Store data collision with DCCM DMA error when address is 0x0
* RAW hazard on mtdata1
* Errors on DMA access could leak into Dbg abstract cmd ocurring at same time
* Icache parity error and branch error collision leading to fwd progress issue
* Fixed linter warning for async reset
# EL2 SweRV RISC-V Core<sup>TM</sup> 1.3 from Western Digital # EL2 SweRV RISC-V Core<sup>TM</sup> 1.3 from Western Digital
@ -8,10 +23,10 @@
* Significantly lower power in sleep as well as normal operation. * Significantly lower power in sleep as well as normal operation.
* Enhanced debug memory abstract command to access internal as well as external memories * Enhanced debug memory abstract command to access internal as well as external memories
* Added bit-manipulation support for Zba, Zbb, Zbc, Zbe, Zbf, Zbp, Zbr, Zbs (Jan 29, 2020 Draft spec). * Added bit-manipulation support for Zba, Zbb, Zbc, Zbe, Zbf, Zbp, Zbr, Zbs (Jan 29, 2020 Draft spec).
* Zbs and Zbb are enabled by default. Use -set=bitmanip+zb*=1 to enable other sub-extensions. * Zbs and Zbb are enabled by default. Use `-set=bitmanip_zb*=1` to enable other sub-extensions.
* Enhancements and additional configurations options for a faster divider * Enhancements and additional configurations options for a faster divider
* JTAG controller intial state issue fixed * JTAG bypass register intial state issue fixed
* Branch predictor fully-associative mode for 8,16,32 entries. * New branch predictor fully-associative option with 8,16,32 entries.
* Corner case bugs fixes related to * Corner case bugs fixes related to
* Bus protocol corner cases (ahb) * Bus protocol corner cases (ahb)
* Fetch bus error recording improved accuracy * Fetch bus error recording improved accuracy
@ -25,7 +40,7 @@
* Handling bigger test sizes using associative arrays in external memory slaves, * Handling bigger test sizes using associative arrays in external memory slaves,
* simplified test building process and CCM loading functions (only program.hex is generated, no data.hex) * simplified test building process and CCM loading functions (only program.hex is generated, no data.hex)
* Improved Makefile and example tests (see README) * Improved Makefile and example tests (see README)
* Generating crt0 and link.ld from swerv.config * Generating link.ld with swerv.config
# EL2 SweRV RISC-V Core<sup>TM</sup> 1.2 from Western Digital # EL2 SweRV RISC-V Core<sup>TM</sup> 1.2 from Western Digital
## Release Notes ## Release Notes

2
testbench/asm/printf.c
View File

@ -31,6 +31,8 @@ whisperPuts(const char* s)
{ {
while (*s) while (*s)
whisperPutc(*s++); whisperPutc(*s++);
whisperPutc('\n');
// whisperPutc(0xd);
return 1; return 1;
} }

251
testbench/dasm.svi
View File

@ -15,39 +15,40 @@
// //
// Run time disassembler functions // Run time disassembler functions
// supports RISCV extentions I, C, M // supports RISCV extentions I, C, M, A
`ifndef RV_NUM_THREADS
`define RV_NUM_THREADS 1
`endif
bit[31:0] gpr[32]; bit[31:0] [31:0] gpr[`RV_NUM_THREADS];
// main DASM function // main DASM function
function string dasm(input[31:0] opcode, input[31:0] pc, input[4:0] regn, input[31:0] regv); function string dasm(input[31:0] opcode, input[31:0] pc, input[4:0] regn, input[31:0] regv, input tid=0);
if(regn) gpr[regn] = regv; dasm = (opcode[1:0] == 2'b11) ? dasm32(opcode, pc, tid) : dasm16(opcode, pc, tid);
if(regn) gpr[tid][regn] = regv;
if( opcode[1:0] == 2'b11 ) return dasm32(opcode, pc);
else return dasm16(opcode, pc);
endfunction endfunction
///////////////// 16 bits instructions /////////////////////// ///////////////// 16 bits instructions ///////////////////////
function string dasm16( input[31:0] opcode, input[31:0] pc); function string dasm16( input[31:0] opcode, input[31:0] pc, input tid=0);
case(opcode[1:0]) case(opcode[1:0])
0: return dasm16_0(opcode); 0: return dasm16_0(opcode, tid);
1: return dasm16_1(opcode, pc); 1: return dasm16_1(opcode, pc);
2: return dasm16_2(opcode); 2: return dasm16_2(opcode);
endcase endcase
return $sformatf(".short 0x%h", opcode[15:0]); return $sformatf(".short 0x%h", opcode[15:0]);
endfunction endfunction
function string dasm16_0( input[31:0] opcode); function string dasm16_0( input[31:0] opcode, tid);
case(opcode[15:13]) case(opcode[15:13])
3'b000: return dasm16_ciw(opcode); 3'b000: return dasm16_ciw(opcode);
3'b001: return {"c.fld", dasm16_cl(opcode)}; 3'b001: return {"c.fld ", dasm16_cl(opcode, tid)};
3'b010: return {"c.lw", dasm16_cl(opcode)}; 3'b010: return {"c.lw ", dasm16_cl(opcode, tid)};
3'b011: return {"c.flw", dasm16_cl(opcode)}; 3'b011: return {"c.flw ", dasm16_cl(opcode, tid)};
3'b101: return {"c.fsd", dasm16_cl(opcode)}; 3'b101: return {"c.fsd ", dasm16_cl(opcode, tid)};
3'b110: return {"c.sw", dasm16_cl(opcode)}; 3'b110: return {"c.sw ", dasm16_cl(opcode, tid)};
3'b111: return {"c.fsw", dasm16_cl(opcode)}; 3'b111: return {"c.fsw ", dasm16_cl(opcode, tid)};
endcase endcase
return $sformatf(".short 0x%h", opcode[15:0]); return $sformatf(".short 0x%h", opcode[15:0]);
endfunction endfunction
@ -57,28 +58,28 @@ int imm;
imm=0; imm=0;
if(opcode[15:0] == 0) return ".short 0"; if(opcode[15:0] == 0) return ".short 0";
{imm[5:4],imm[9:6],imm[2],imm[3]} = opcode[12:5]; {imm[5:4],imm[9:6],imm[2],imm[3]} = opcode[12:5];
return $sformatf("c.addi4spn %s, 0x%0h", abi_reg[opcode[4:2]+8], imm); return $sformatf("c.addi4spn %s,0x%0h", abi_reg[opcode[4:2]+8], imm);
endfunction endfunction
function string dasm16_cl( input[31:0] opcode); function string dasm16_cl( input[31:0] opcode, input tid=0);
int imm; int imm;
imm=0; imm=0;
imm[5:3] = opcode[12:10]; imm[5:3] = opcode[12:10];
imm[7:6] = opcode[6:5]; imm[7:6] = opcode[6:5];
return $sformatf(" %s, %0d(%s) [%h]", abi_reg[opcode[4:2]+8], imm, abi_reg[opcode[9:7]+8], gpr[opcode[9:7]+8]+imm); return $sformatf(" %s,%0d(%s) [%h]", abi_reg[opcode[4:2]+8], imm, abi_reg[opcode[9:7]+8], gpr[tid][opcode[9:7]+8]+imm);
endfunction endfunction
function string dasm16_1( input[31:0] opcode, input[31:0] pc); function string dasm16_1( input[31:0] opcode, input[31:0] pc);
case(opcode[15:13]) case(opcode[15:13])
3'b000: return opcode[11:7]==0 ? "c.nop" : {"c.addi",dasm16_ci(opcode)}; 3'b000: return opcode[11:7]==0 ? "c.nop" : {"c.addi ",dasm16_ci(opcode)};
3'b001: return {"c.jal", dasm16_cj(opcode, pc)}; 3'b001: return {"c.jal ", dasm16_cj(opcode, pc)};
3'b010: return {"c.li", dasm16_ci(opcode)}; 3'b010: return {"c.li ", dasm16_ci(opcode)};
3'b011: return dasm16_1_3(opcode); 3'b011: return dasm16_1_3(opcode);
3'b100: return dasm16_cr(opcode); 3'b100: return dasm16_cr(opcode);
3'b101: return {"c.j", dasm16_cj(opcode, pc)}; 3'b101: return {"c.j ", dasm16_cj(opcode, pc)};
3'b110: return {"c.beqz", dasm16_cb(opcode, pc)}; 3'b110: return {"c.beqz ", dasm16_cb(opcode, pc)};
3'b111: return {"c.bnez", dasm16_cb(opcode, pc)}; 3'b111: return {"c.bnez ", dasm16_cb(opcode, pc)};
endcase endcase
endfunction endfunction
@ -87,7 +88,7 @@ int imm;
imm=0; imm=0;
imm[4:0] = opcode[6:2]; imm[4:0] = opcode[6:2];
if(opcode[12]) imm [31:5] = '1; if(opcode[12]) imm [31:5] = '1;
return $sformatf(" %s, %0d", abi_reg[opcode[11:7]], imm); return $sformatf("%s,%0d", abi_reg[opcode[11:7]], imm);
endfunction endfunction
function string dasm16_cj( input[31:0] opcode, input[31:0] pc); function string dasm16_cj( input[31:0] opcode, input[31:0] pc);
@ -95,16 +96,16 @@ bit[31:0] imm;
imm=0; imm=0;
{imm[11],imm[4],imm[9:8],imm[10],imm[6], imm[7],imm[3:1], imm[5]} = opcode[12:2]; {imm[11],imm[4],imm[9:8],imm[10],imm[6], imm[7],imm[3:1], imm[5]} = opcode[12:2];
if(opcode[12]) imm [31:12] = '1; if(opcode[12]) imm [31:12] = '1;
return $sformatf(" 0x%h", imm+pc); return $sformatf("0x%0h", imm+pc);
endfunction endfunction
function string dasm16_cb( input[31:0] opcode, input[31:0] pc); function string dasm16_cb( input[31:0] opcode, input[31:0] pc);
bit[31:0] imm; bit[31:0] imm;
imm=0; imm=0;
{imm[11],imm[4:3]} = opcode[12:10]; {imm[8],imm[4:3]} = opcode[12:10];
{imm[7], imm[6],imm[2:1], imm[5]} = opcode[6:2]; {imm[7:6],imm[2:1], imm[5]} = opcode[6:2];
if(opcode[12]) imm [31:9] = '1; if(opcode[12]) imm [31:9] = '1;
return $sformatf(" %s, 0x%h",abi_reg[opcode[9:7]+8], imm+pc); return $sformatf("%s,0x%0h",abi_reg[opcode[9:7]+8], imm+pc);
endfunction endfunction
function string dasm16_cr( input[31:0] opcode); function string dasm16_cr( input[31:0] opcode);
@ -114,16 +115,16 @@ bit[31:0] imm;
imm[4:0] = opcode[6:2]; imm[4:0] = opcode[6:2];
if(opcode[5]) imm [31:5] = '1; if(opcode[5]) imm [31:5] = '1;
case(opcode[11:10]) case(opcode[11:10])
0: return $sformatf("c.srli %s, %0d", abi_reg[opcode[9:7]+8], imm[5:0]); 0: return $sformatf("c.srli %s,%0d", abi_reg[opcode[9:7]+8], imm[5:0]);
1: return $sformatf("c.srai %s, %0d", abi_reg[opcode[9:7]+8], imm[5:0]); 1: return $sformatf("c.srai %s,%0d", abi_reg[opcode[9:7]+8], imm[5:0]);
2: return $sformatf("c.andi %s, 0x%h", abi_reg[opcode[9:7]+8], imm); 2: return $sformatf("c.andi %s,0x%0h", abi_reg[opcode[9:7]+8], imm);
endcase endcase
case(opcode[6:5]) case(opcode[6:5])
0: return $sformatf("c.sub %s, %s", abi_reg[opcode[9:7]+8], abi_reg[opcode[4:2]+8]); 0: return $sformatf("c.sub %s,%s", abi_reg[opcode[9:7]+8], abi_reg[opcode[4:2]+8]);
1: return $sformatf("c.xor %s, %s", abi_reg[opcode[9:7]+8], abi_reg[opcode[4:2]+8]); 1: return $sformatf("c.xor %s,%s", abi_reg[opcode[9:7]+8], abi_reg[opcode[4:2]+8]);
2: return $sformatf("c.or %s, %s", abi_reg[opcode[9:7]+8], abi_reg[opcode[4:2]+8]); 2: return $sformatf("c.or %s,%s", abi_reg[opcode[9:7]+8], abi_reg[opcode[4:2]+8]);
3: return $sformatf("c.and %s, %s", abi_reg[opcode[9:7]+8], abi_reg[opcode[4:2]+8]); 3: return $sformatf("c.and %s,%s", abi_reg[opcode[9:7]+8], abi_reg[opcode[4:2]+8]);
endcase endcase
endfunction endfunction
@ -137,68 +138,68 @@ int imm;
return $sformatf("c.addi16sp %0d", imm); return $sformatf("c.addi16sp %0d", imm);
end end
else begin else begin
// {imm[4], imm[6],imm[8:7], imm[5]} = opcode[6:2];
imm[16:12] = opcode[6:2]; imm[16:12] = opcode[6:2];
if(opcode[12]) imm [31:17] = '1; if(opcode[12]) imm [31:17] = '1;
return $sformatf("c.lui %3s, 0x%h", abi_reg[opcode[11:7]], imm); return $sformatf("c.lui %s,0x%0h", abi_reg[opcode[11:7]], imm);
end end
endfunction endfunction
function string dasm16_2( input[31:0] opcode); function string dasm16_2( input[31:0] opcode, input tid=0);
case(opcode[15:13]) case(opcode[15:13])
3'b000: return {"c.slli", dasm16_ci(opcode)}; 3'b000: return {"c.slli ", dasm16_ci(opcode)};
3'b001: return {"c.fldsp", dasm16_cls(opcode,1)}; 3'b001: return {"c.fldsp ", dasm16_cls(opcode,1,tid)};
3'b010: return {"c.lwsp", dasm16_cls(opcode)}; 3'b010: return {"c.lwsp ", dasm16_cls(opcode,0,tid)};
3'b011: return {"c.flwsp", dasm16_cls(opcode)}; 3'b011: return {"c.flwsp ", dasm16_cls(opcode,0,tid)};
3'b101: return {"c.fsdsp", dasm16_css(opcode,1)}; 3'b101: return {"c.fsdsp ", dasm16_css(opcode,1,tid)};
3'b110: return {"c.swsp", dasm16_css(opcode)}; 3'b110: return {"c.swsp ", dasm16_css(opcode,0,tid)};
3'b111: return {"c.fswsp", dasm16_css(opcode)}; 3'b111: return {"c.fswsp ", dasm16_css(opcode,0,tid)};
endcase endcase
if(opcode[12]) begin if(opcode[12]) begin
if(opcode[12:2] == 0) return "c.ebreak"; if(opcode[12:2] == 0) return "c.ebreak";
else if(opcode[6:2] == 0) return $sformatf("c.jalr %s", abi_reg[opcode[11:7]]); else if(opcode[6:2] == 0) return $sformatf("c.jalr %s", abi_reg[opcode[11:7]]);
else return $sformatf("c.add %s, %s", abi_reg[opcode[11:7]], abi_reg[opcode[6:2]]); else return $sformatf("c.add %s,%s", abi_reg[opcode[11:7]], abi_reg[opcode[6:2]]);
end end
else begin else begin
if(opcode[6:2] == 0) return $sformatf("c.jr %s", abi_reg[opcode[11:7]]); if(opcode[6:2] == 0) return $sformatf("c.jr %s", abi_reg[opcode[11:7]]);
else return $sformatf("c.mv %s, %s", abi_reg[opcode[11:7]], abi_reg[opcode[6:2]]); else return $sformatf("c.mv %s,%s", abi_reg[opcode[11:7]], abi_reg[opcode[6:2]]);
end end
endfunction endfunction
function string dasm16_cls( input[31:0] opcode, input sh1=0); function string dasm16_cls( input[31:0] opcode, input sh1=0, tid=0);
bit[31:0] imm; bit[31:0] imm;
imm=0; imm=0;
if(sh1) {imm[4:3],imm[8:6]} = opcode[6:2]; if(sh1) {imm[4:3],imm[8:6]} = opcode[6:2];
else {imm[4:2],imm[7:6]} = opcode[6:2]; else {imm[4:2],imm[7:6]} = opcode[6:2];
imm[5] = opcode[12]; imm[5] = opcode[12];
return $sformatf(" %s, 0x%0h [%h]", abi_reg[opcode[11:7]], imm, gpr[2]+imm); return $sformatf("%s,0x%0h [%h]", abi_reg[opcode[11:7]], imm, gpr[tid][2]+imm);
endfunction endfunction
function string dasm16_css( input[31:0] opcode, input sh1=0); function string dasm16_css( input[31:0] opcode, input sh1=0, tid=0);
bit[31:0] imm; bit[31:0] imm;
imm=0; imm=0;
if(sh1) {imm[5:3],imm[8:6]} = opcode[12:7]; if(sh1) {imm[5:3],imm[8:6]} = opcode[12:7];
else {imm[5:2],imm[7:6]} = opcode[12:7]; else {imm[5:2],imm[7:6]} = opcode[12:7];
return $sformatf(" %s, 0x%0h [%h]", abi_reg[opcode[6:2]], imm, gpr[2]+imm); return $sformatf("%s,0x%0h [%h]", abi_reg[opcode[6:2]], imm, gpr[tid][2]+imm);
endfunction endfunction
///////////////// 32 bit instructions /////////////////////// ///////////////// 32 bit instructions ///////////////////////
function string dasm32( input[31:0] opcode, input[31:0] pc); function string dasm32( input[31:0] opcode, input[31:0] pc, input tid=0);
case(opcode[6:0]) case(opcode[6:0])
7'b0110111: return {"lui", dasm32_u(opcode)}; 7'b0110111: return {"lui ", dasm32_u(opcode)};
7'b0010111: return {"auipc", dasm32_u(opcode)}; 7'b0010111: return {"auipc ", dasm32_u(opcode)};
7'b1101111: return {"jal", dasm32_j(opcode,pc)}; 7'b1101111: return {"jal ", dasm32_j(opcode,pc)};
7'b1100111: return {"jalr", dasm32_jr(opcode,pc)}; 7'b1100111: return {"jalr ", dasm32_jr(opcode,pc)};
7'b1100011: return dasm32_b(opcode,pc); 7'b1100011: return dasm32_b(opcode,pc);
7'b0000011: return dasm32_l(opcode); 7'b0000011: return dasm32_l(opcode,tid);
7'b0100011: return dasm32_s(opcode); 7'b0100011: return dasm32_s(opcode,tid);
7'b0010011: return dasm32_ai(opcode); 7'b0010011: return dasm32_ai(opcode);
7'b0110011: return dasm32_ar(opcode); 7'b0110011: return dasm32_ar(opcode);
7'b0001111: return {"fence", dasm32_fence(opcode)}; 7'b0001111: return {"fence", dasm32_fence(opcode)};
7'b1110011: return dasm32_e(opcode); 7'b1110011: return dasm32_e(opcode);
7'b0101111: return dasm32_a(opcode,tid);
endcase endcase
return $sformatf(".long 0x%h", opcode); return $sformatf(".long 0x%h", opcode);
@ -208,7 +209,7 @@ function string dasm32_u( input[31:0] opcode);
bit[31:0] imm; bit[31:0] imm;
imm=0; imm=0;
imm[31:12] = opcode[31:12]; imm[31:12] = opcode[31:12];
return $sformatf(" %s, 0x%0h", abi_reg[opcode[11:7]], imm); return $sformatf("%s,0x%0h", abi_reg[opcode[11:7]], imm);
endfunction endfunction
function string dasm32_j( input[31:0] opcode, input[31:0] pc); function string dasm32_j( input[31:0] opcode, input[31:0] pc);
@ -216,7 +217,7 @@ int imm;
imm=0; imm=0;
{imm[20], imm[10:1], imm[11], imm[19:12]} = opcode[31:12]; {imm[20], imm[10:1], imm[11], imm[19:12]} = opcode[31:12];
if(opcode[31]) imm[31:20] = '1; if(opcode[31]) imm[31:20] = '1;
return $sformatf(" %s, 0x%0h",abi_reg[opcode[11:7]], imm+pc); return $sformatf("%s,0x%0h",abi_reg[opcode[11:7]], imm+pc);
endfunction endfunction
function string dasm32_jr( input[31:0] opcode, input[31:0] pc); function string dasm32_jr( input[31:0] opcode, input[31:0] pc);
@ -224,7 +225,7 @@ int imm;
imm=0; imm=0;
imm[11:1] = opcode[31:19]; imm[11:1] = opcode[31:19];
if(opcode[31]) imm[31:12] = '1; if(opcode[31]) imm[31:12] = '1;
return $sformatf(" %s, %s, 0x%0h",abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm+pc); return $sformatf("%s,%s,0x%0h",abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm+pc);
endfunction endfunction
function string dasm32_b( input[31:0] opcode, input[31:0] pc); function string dasm32_b( input[31:0] opcode, input[31:0] pc);
@ -235,35 +236,35 @@ string mn;
{imm[4:1],imm[11]} = opcode[11:7]; {imm[4:1],imm[11]} = opcode[11:7];
if(opcode[31]) imm[31:12] = '1; if(opcode[31]) imm[31:12] = '1;
case(opcode[14:12]) case(opcode[14:12])
0: mn = "beq"; 0: mn = "beq ";
1: mn = "bne"; 1: mn = "bne ";
2,3 : return $sformatf(".long 0x%h", opcode); 2,3 : return $sformatf(".long 0x%h", opcode);
4: mn = "blt"; 4: mn = "blt ";
5: mn = "bge"; 5: mn = "bge ";
6: mn = "bltu"; 6: mn = "bltu ";
7: mn = "bgeu"; 7: mn = "bgeu ";
endcase endcase
return $sformatf("%s %s, %s, 0x%0h", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm+pc); return $sformatf("%s%s,%s,0x%0h", mn, abi_reg[opcode[19:15]], abi_reg[opcode[24:20]], imm+pc);
endfunction endfunction
function string dasm32_l( input[31:0] opcode); function string dasm32_l( input[31:0] opcode, input tid=0);
int imm; int imm;
string mn; string mn;
imm=0; imm=0;
imm[11:0] = opcode[31:20]; imm[11:0] = opcode[31:20];
if(opcode[31]) imm[31:12] = '1; if(opcode[31]) imm[31:12] = '1;
case(opcode[14:12]) case(opcode[14:12])
0: mn = "lb"; 0: mn = "lb ";
1: mn = "lh"; 1: mn = "lh ";
2: mn = "lw"; 2: mn = "lw ";
4: mn = "lbu"; 4: mn = "lbu ";
5: mn = "lhu"; 5: mn = "lhu ";
default : return $sformatf(".long 0x%h", opcode); default : return $sformatf(".long 0x%h", opcode);
endcase endcase
return $sformatf("%s %s, %0d(%s) [%h]", mn, abi_reg[opcode[11:7]], imm, abi_reg[opcode[19:15]], imm+gpr[opcode[19:15]]); return $sformatf("%s%s,%0d(%s) [%h]", mn, abi_reg[opcode[11:7]], imm, abi_reg[opcode[19:15]], imm+gpr[tid][opcode[19:15]]);
endfunction endfunction
function string dasm32_s( input[31:0] opcode); function string dasm32_s( input[31:0] opcode, input tid=0);
int imm; int imm;
string mn; string mn;
imm=0; imm=0;
@ -271,12 +272,12 @@ string mn;
imm[4:0] = opcode[11:7]; imm[4:0] = opcode[11:7];
if(opcode[31]) imm[31:12] = '1; if(opcode[31]) imm[31:12] = '1;
case(opcode[14:12]) case(opcode[14:12])
0: mn = "sb"; 0: mn = "sb ";
1: mn = "sh"; 1: mn = "sh ";
2: mn = "sw"; 2: mn = "sw ";
default : return $sformatf(".long 0x%h", opcode); default : return $sformatf(".long 0x%h", opcode);
endcase endcase
return $sformatf("%s %s, %0d(%s) [%h]", mn, abi_reg[opcode[24:20]], imm, abi_reg[opcode[19:15]], imm+gpr[opcode[19:15]]); return $sformatf("%s%s,%0d(%s) [%h]", mn, abi_reg[opcode[24:20]], imm, abi_reg[opcode[19:15]], imm+gpr[tid][opcode[19:15]]);
endfunction endfunction
function string dasm32_ai( input[31:0] opcode); function string dasm32_ai( input[31:0] opcode);
@ -286,16 +287,16 @@ string mn;
imm[11:0] = opcode[31:20]; imm[11:0] = opcode[31:20];
if(opcode[31]) imm[31:12] = '1; if(opcode[31]) imm[31:12] = '1;
case(opcode[14:12]) case(opcode[14:12])
0: mn = "addi"; 0: mn = "addi ";
2: mn = "slti"; 2: mn = "slti ";
3: mn = "sltiu"; 3: mn = "sltiu ";
4: mn = "xori"; 4: mn = "xori ";
6: mn = "ori"; 6: mn = "ori ";
7: mn = "andi"; 7: mn = "andi ";
default: return dasm32_si(opcode); default: return dasm32_si(opcode);
endcase endcase
return $sformatf("%s %s, %s, %0d", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm); return $sformatf("%s%s,%s,%0d", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm);
endfunction endfunction
function string dasm32_si( input[31:0] opcode); function string dasm32_si( input[31:0] opcode);
@ -307,7 +308,7 @@ string mn;
5: mn = opcode[30] ? "srli": "srai"; 5: mn = opcode[30] ? "srli": "srai";
endcase endcase
return $sformatf("%s %s, %s, %0d", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm); return $sformatf("%s %s,%s,%0d", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], imm);
endfunction endfunction
@ -316,27 +317,27 @@ function string dasm32_ar( input[31:0] opcode);
string mn; string mn;
if(opcode[25]) if(opcode[25])
case(opcode[14:12]) case(opcode[14:12])
0: mn = "mul"; 0: mn = "mul ";
1: mn = "mulh"; 1: mn = "mulh ";
2: mn = "mulhsu"; 2: mn = "mulhsu ";
3: mn = "mulhu"; 3: mn = "mulhu ";
4: mn = "div"; 4: mn = "div ";
5: mn = "divu"; 5: mn = "divu ";
6: mn = "rem"; 6: mn = "rem ";
7: mn = "remu"; 7: mn = "remu ";
endcase endcase
else else
case(opcode[14:12]) case(opcode[14:12])
0: mn = opcode[30]? "sub":"add"; 0: mn = opcode[30]? "sub ":"add ";
1: mn = "sll"; 1: mn = "sll ";
2: mn = "slt"; 2: mn = "slt ";
3: mn = "sltu"; 3: mn = "sltu ";
4: mn = "xor"; 4: mn = "xor ";
5: mn = opcode[30]? "sra" :"srl"; 5: mn = opcode[30]? "sra ":"srl ";
6: mn = "or"; 6: mn = "or ";
7: mn = "and"; 7: mn = "and ";
endcase endcase
return $sformatf("%s %s, %s, %s", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], abi_reg[opcode[24:20]]); return $sformatf("%s%s,%s,%s", mn, abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], abi_reg[opcode[24:20]]);
endfunction endfunction
function string dasm32_fence( input[31:0] opcode); function string dasm32_fence( input[31:0] opcode);
@ -348,12 +349,12 @@ function string dasm32_e(input[31:0] opcode);
else if({opcode[31:21],opcode [19:7]} == 0) return "ebreak"; else if({opcode[31:21],opcode [19:7]} == 0) return "ebreak";
else else
case(opcode[14:12]) case(opcode[14:12])
1: return {"csrrw", dasm32_csr(opcode)}; 1: return {"csrrw ", dasm32_csr(opcode)};
2: return {"csrrs", dasm32_csr(opcode)}; 2: return {"csrrs ", dasm32_csr(opcode)};
3: return {"csrrc", dasm32_csr(opcode)}; 3: return {"csrrc ", dasm32_csr(opcode)};
5: return {"csrrwi", dasm32_csr(opcode, 1)}; 5: return {"csrrwi ", dasm32_csr(opcode, 1)};
6: return {"csrrsi", dasm32_csr(opcode, 1)}; 6: return {"csrrsi ", dasm32_csr(opcode, 1)};
7: return {"csrrci", dasm32_csr(opcode, 1)}; 7: return {"csrrci ", dasm32_csr(opcode, 1)};
endcase endcase
endfunction endfunction
@ -363,12 +364,32 @@ function string dasm32_csr(input[31:0] opcode, input im=0);
bit[11:0] csr; bit[11:0] csr;
csr = opcode[31:20]; csr = opcode[31:20];
if(im) begin if(im) begin
return $sformatf(" %s, csr_%0h, 0x%h", abi_reg[opcode[11:7]], csr, opcode[19:15]); return $sformatf("%s,csr_%0h,0x%h", abi_reg[opcode[11:7]], csr, opcode[19:15]);
end end
else begin else begin
return $sformatf(" %s, csr_%0h, %s", abi_reg[opcode[11:7]], csr, abi_reg[opcode[19:15]]); return $sformatf("%s,csr_%0h,%s", abi_reg[opcode[11:7]], csr, abi_reg[opcode[19:15]]);
end end
endfunction endfunction
//atomics
function string dasm32_a(input[31:0] opcode, input tid=0);
case(opcode[31:27])
'b00010: return $sformatf("lr.w %s,(%s) [%h]", abi_reg[opcode[11:7]], abi_reg[opcode[19:15]], gpr[tid][opcode[19:15]]);
'b00011: return $sformatf("sc.w %s,%s,(%s) [%h]", abi_reg[opcode[11:7]], abi_reg[opcode[24:20]], abi_reg[opcode[19:15]], gpr[tid][opcode[19:15]]);
'b00001: return {"amoswap.w", dasm32_amo(opcode, tid)};
'b00000: return {"amoadd.w", dasm32_amo(opcode, tid)};
'b00100: return {"amoxor.w", dasm32_amo(opcode, tid)};
'b01100: return {"amoand.w", dasm32_amo(opcode, tid)};
'b01000: return {"amoor.w", dasm32_amo(opcode, tid)};
'b10000: return {"amomin.w", dasm32_amo(opcode, tid)};
'b10100: return {"amomax.w", dasm32_amo(opcode, tid)};
'b11000: return {"amominu.w", dasm32_amo(opcode, tid)};
'b11100: return {"amomaxu.w", dasm32_amo(opcode, tid)};
endcase
return $sformatf(".long 0x%h", opcode);
endfunction
function string dasm32_amo( input[31:0] opcode, input tid=0);
return $sformatf(" %s,%s,(%s) [%h]", abi_reg[opcode[11:7]], abi_reg[opcode[24:20]], abi_reg[opcode[19:15]], gpr[tid][opcode[19:15]]);
endfunction

4155
testbench/hex/cmark_dccm.hex
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File diff suppressed because it is too large Load Diff

8
testbench/hex/data.hex
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@ -1,8 +0,0 @@
@00001000
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
2D 2D 0A 48 65 6C 6C 6F 20 57 6F 72 6C 64 20 66
72 6F 6D 20 53 77 65 52 56 20 45 4C 32 20 40 57
44 43 20 21 21 0A 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
2D 2D 2D 2D 2D 2D 2D 2D 0A 00

317
testbench/hex/dhry.hex Normal file
View File

@ -0,0 +1,317 @@
@80000000
B7 52 55 59 93 82 52 55 73 90 02 7C 17 41 04 70
13 01 41 E2 97 00 00 6E E7 80 C0 69 97 02 58 50
93 82 42 FE 13 03 F0 0F 23 80 62 00 05 43 23 A0
62 00 E3 05 00 FE 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00
@D0580000
00 00 00 00
@EE000000
41 11 4A C0 37 39 04 F0 83 27 09 D5 22 C4 00 41
94 43 03 AF 47 00 83 AE 87 00 03 AE 07 01 03 A3
47 01 83 A8 87 01 03 A8 C7 01 90 57 D8 57 CC 53
06 C6 26 C2 AA 84 88 53 14 C0 94 40 23 22 E4 01
23 24 D4 01 23 28 C4 01 23 2A 64 00 23 2C 14 01
23 2E 04 01 08 D0 10 D4 58 D4 4C D0 15 47 D8 C4
14 C0 9C 43 B7 36 04 F0 83 A5 86 D4 1C C0 03 26
09 D5 58 C4 29 45 31 06 99 22 5C 40 A1 CF 9C 40
B2 40 22 44 03 AF 07 00 83 AE 47 00 03 AE 87 00
03 A3 C7 00 83 A8 07 01 03 A8 47 01 88 4F CC 4F
90 53 D4 53 98 57 DC 57 23 A0 E4 01 23 A2 D4 01
23 A4 C4 01 23 A6 64 00 23 A8 14 01 23 AA 04 01
88 CC CC CC 90 D0 D4 D0 98 D4 DC D4 02 49 92 44
41 01 82 80 88 44 99 47 93 05 84 00 5C C4 55 20
83 27 09 D5 48 44 13 06 C4 00 9C 43 B2 40 92 44
1C C0 22 44 02 49 A9 45 41 01 D1 A0 B7 37 04 F0
03 C7 C7 D4 93 07 10 04 63 03 F7 00 82 80 1C 41
37 37 04 F0 03 27 87 D4 A5 07 99 8F 1C C1 82 80
B7 37 04 F0 03 A6 07 D5 09 C6 18 42 18 C1 03 A6
07 D5 B7 37 04 F0 83 A5 87 D4 31 06 29 45 41 A0
B7 37 04 F0 83 C7 C7 D4 37 37 04 F0 83 26 C7 E1
93 87 F7 FB 93 B7 17 00 D5 8F 23 2E F7 E0 B7 37
04 F0 13 07 20 04 A3 86 E7 D4 82 80 B7 37 04 F0
13 07 10 04 23 86 E7 D4 B7 37 04 F0 23 AE 07 E0
82 80 09 47 63 0A E5 02 8D 47 9C C1 85 47 63 09
F5 00 63 FF A7 00 91 47 63 1F F5 00 98 C1 82 80
B7 37 04 F0 03 A7 87 D4 93 07 40 06 E3 D9 E7 FE
23 A0 05 00 82 80 82 80 85 47 9C C1 82 80 09 05
2E 95 08 C2 82 80 13 07 56 00 13 08 80 0C 33 08
07 03 93 17 27 00 0A 06 3E 95 14 C1 38 DD 54 C1
B3 07 C8 00 AE 97 94 4B D8 CB 98 CF 13 87 16 00
98 CB 18 41 C2 95 85 67 B2 95 BE 95 23 AA E5 FA
B7 37 04 F0 15 47 23 A4 E7 D4 82 80 13 75 F5 0F
93 F5 F5 0F 63 04 B5 00 01 45 82 80 B7 37 04 F0
23 86 A7 D4 05 45 82 80 03 47 25 00 83 C7 35 00
63 02 F7 02 41 11 06 C6 A9 2E 81 47 63 58 A0 00
B7 37 04 F0 29 47 23 A4 E7 D4 85 47 B2 40 3E 85
41 01 82 80 01 A0 79 15 13 35 15 00 82 80 03 48
05 00 63 0B 08 28 39 71 22 DE 37 04 04 F0 26 DC
4A DA 4E D8 52 D6 AA 86 56 D4 5A D2 5E D0 01 45
93 0F 50 02 B7 08 58 D0 13 03 00 03 93 09 D0 02
13 09 A0 02 93 04 00 02 13 04 04 00 29 4F 93 03
B1 00 A5 42 13 0A D0 02 03 C6 16 00 93 87 16 00
63 03 F8 03 23 80 08 01 05 05 BE 86 32 88 E3 15
08 FE 72 54 E2 54 52 59 C2 59 32 5A A2 5A 12 5B
82 5B 21 61 82 80 75 D6 13 8E 26 00 63 00 F6 07
63 1D 66 1E 03 C7 17 00 BE 86 85 07 E3 0C 67 FE
89 06 03 C8 17 00 63 05 37 03 63 0A 27 03 93 0A
07 FD 13 FE FA 0F 81 4E 63 F2 C2 05 13 07 87 FA
13 77 F7 0F E3 E5 E4 FA 0A 07 22 97 1C 43 82 87
42 87 03 C8 27 00 B6 87 85 06 E3 1A 27 FD 42 87
91 05 03 C8 27 00 85 06 81 4E C9 BF 23 80 08 01
03 C8 26 00 F2 86 E3 11 08 F6 A5 BF 03 C8 17 00
19 A0 93 0A 07 FD 13 9E 2E 00 76 9E 93 06 08 FD
3E 8B 06 0E 85 07 93 F6 F6 0F 42 87 B3 8E CA 01
03 C8 17 00 E3 FF D2 FC 93 06 2B 00 41 BF 98 41
81 47 91 05 11 A0 B2 87 93 7E F7 00 13 8E 7E 05
63 C4 D2 01 13 8E 0E 03 13 86 17 00 93 0E C1 00
B2 9E A3 8F CE FF 11 83 79 FF 78 00 BA 97 03 C7
07 00 FD 17 23 80 E8 00 E3 9B F3 FE 32 95 E3 15
08 EE 01 B7 03 AE 05 00 01 47 91 05 B3 7A EE 03
13 0B C1 00 BA 87 05 07 B3 0B EB 00 72 8B 93 8A
0A 03 A3 8F 5B FF 33 5E EE 03 E3 E1 62 FF 3A 8E
63 57 D7 01 23 80 C8 00 05 0E E3 9D CE FF 70 00
B2 97 03 C6 07 00 FD 17 23 80 C8 00 E3 9B 77 FE
3A 95 E3 1B 08 E8 75 B5 98 41 91 05 83 47 07 00
99 C7 05 07 23 80 F8 00 83 47 07 00 FD FB 23 80
E8 01 05 05 E3 1A 08 E6 69 B5 90 41 01 47 91 05
13 7E 76 00 BA 87 93 0E C1 00 05 07 BA 9E 13 0E
0E 03 A3 8F CE FF 0D 82 65 F6 70 00 B2 97 03 C6
07 00 FD 17 23 80 C8 00 E3 9B 77 FE 3A 95 55 B7
83 AB 05 00 91 05 5E 87 63 CA 0B 06 81 47 33 6E
E7 03 3E 8B 93 0A C1 00 85 07 BE 9A 33 47 E7 03
13 0E 0E 03 A3 8F CA FF 7D F3 3E 87 63 D7 D7 01
23 80 C8 00 05 07 E3 1D D7 FF 78 00 5A 97 03 46
07 00 7D 17 23 80 C8 00 E3 1B 77 FE 63 C4 0B 02
3E 95 E3 13 08 DE F5 BB 83 C7 05 00 05 05 91 05
23 80 F8 00 E3 1A 08 DC ED B3 32 87 F2 86 13 06
00 02 01 BD 93 07 2B 00 3E 95 E1 BF 33 07 70 41
23 80 48 01 FD 1E 59 B7 01 45 82 80 39 71 13 03
41 02 2E D2 9A 85 06 CE 32 D4 36 D6 3A D8 3E DA
42 DC 46 DE 1A C6 A1 33 F2 40 21 61 82 80 13 77
F5 0F B7 07 58 D0 23 80 E7 00 3A 85 82 80 13 77
F5 0F B7 07 58 D0 23 80 E7 00 3A 85 82 80 83 47
05 00 37 07 58 D0 99 C7 05 05 23 00 F7 00 83 47
05 00 FD FB A9 47 23 00 F7 00 05 45 82 80 39 71
13 03 41 02 2E D2 9A 85 06 CE 32 D4 36 D6 3A D8
3E DA 42 DC 46 DE 1A C6 DD 31 F2 40 21 61 82 80
F3 25 00 B8 73 25 00 B0 F3 27 00 B8 E3 9A F5 FE
82 80 33 67 B5 00 FD 53 0D 8B 79 E7 B7 87 7F 7F
93 87 F7 F7 10 41 94 41 B3 72 F6 00 33 63 F6 00
BE 92 B3 E2 62 00 63 97 72 0C 63 18 D6 06 50 41
D4 41 B3 72 F6 00 33 63 F6 00 BE 92 B3 E2 62 00
63 98 72 0A 63 1B D6 04 10 45 94 45 B3 72 F6 00
33 63 F6 00 BE 92 B3 E2 62 00 63 91 72 0A 63 1E
D6 02 50 45 D4 45 B3 72 F6 00 33 63 F6 00 BE 92
B3 E2 62 00 63 9A 72 08 63 11 D6 02 10 49 94 49
B3 72 F6 00 33 63 F6 00 BE 92 B3 E2 62 00 63 93
72 08 51 05 D1 05 E3 0F D6 F6 13 17 06 01 93 97
06 01 63 1C F7 00 13 57 06 01 93 D7 06 01 33 05
F7 40 93 75 F5 0F 91 E9 82 80 41 83 C1 83 33 05
F7 40 93 75 F5 0F 91 E1 82 80 13 77 F7 0F 93 F7
F7 0F 33 05 F7 40 82 80 03 46 05 00 83 C6 05 00
05 05 85 05 63 13 D6 00 65 FA 33 05 D6 40 82 80
11 05 91 05 E3 12 D6 FE 01 45 82 80 21 05 A1 05
E3 1C D6 FC 01 45 82 80 31 05 B1 05 E3 16 D6 FC
01 45 82 80 41 05 C1 05 E3 10 D6 FC 01 45 82 80
@EE0006B0
37 07 04 F0 6D 71 13 07 C7 59 B7 07 04 F0 93 87
C7 5B 03 2F 07 00 83 2E 47 00 03 2E 87 00 DA D9
93 0F 01 0A 37 3B 04 F0 83 28 07 01 03 28 47 01
08 4F 83 55 C7 01 03 46 E7 01 94 43 03 23 C7 00
23 28 FB D5 D8 43 89 4F 23 24 81 10 23 22 91 10
7E D5 84 18 93 0F 80 02 37 34 04 F0 23 26 11 10
E2 D5 7E D7 7A D9 76 DB 72 DD 23 20 21 11 CE DF
D2 DD D6 DB DE D7 E6 D3 EA D1 EE CF 23 22 94 D4
26 D1 1A DF C6 C1 C2 C3 83 A8 87 00 03 A8 C7 00
23 16 B1 0C 23 07 C1 0C 8C 4B D0 4B 36 D8 3A DA
94 4F 03 D7 C7 01 83 C7 E7 01 AA C5 37 0C 04 F0
37 05 04 F0 23 16 E1 04 23 07 F1 04 13 07 0C 63
A9 47 13 05 45 08 23 2E F7 64 02 D3 46 DC 42 DE
AE C0 B2 C2 B6 C4 EF F0 9F DB B7 07 04 F0 83 A7
C7 61 63 8B 07 50 37 05 04 F0 13 05 45 0B EF F0
1F DA 37 05 04 F0 93 05 80 3E 13 05 05 11 EF F0
1F DB EF F0 FF DC B7 07 04 F0 23 A6 A7 62 B7 07
04 F0 93 87 C7 5D D8 43 83 AD 07 00 37 08 04 F0
3A C2 98 47 85 44 B7 39 04 F0 3A C4 D8 47 37 3A
04 F0 37 34 04 F0 3A C6 98 4B B7 3B 04 F0 B7 3A
04 F0 3A C8 D8 4B 93 0C C8 5F 3A CA 98 4F 3A CC
03 D7 C7 01 83 C7 E7 01 23 1E E1 00 A3 0F F1 00
13 07 10 04 23 86 E9 D4 13 07 20 04 A3 06 E4 D4
12 47 85 47 8C 08 BA CA 22 47 08 18 23 2E FA E0
BA CC 32 47 3E D6 EE C8 BA CE 42 47 BA D0 52 47
BA D2 62 47 BA D4 03 57 C1 01 23 16 E1 06 03 47
F1 01 23 07 E1 06 EF F0 3F 9D 93 37 15 00 30 10
8D 45 09 45 23 2E FA E0 9D 47 3E D4 EF F0 3F 95
A2 56 0D 46 93 05 0C 63 13 85 4B D5 EF F0 BF 94
03 25 0B D5 EF F0 CF F7 03 47 D4 D4 93 07 00 04
63 F0 E7 3C 13 0D 10 04 0D 49 6A 85 93 05 30 04
EF F0 DF 96 B2 57 13 07 1D 00 63 07 F5 34 83 47
D4 D4 13 7D F7 0F E3 F2 A7 FF 93 17 19 00 3E 99
A2 58 83 C6 C9 D4 13 07 10 04 33 46 19 03 B2 87
63 97 E6 00 03 A7 8A D4 93 07 96 00 99 8F 85 04
13 07 90 3E E3 96 E4 F2 46 C6 32 C4 3E C2 EF F0
3F C9 AA 85 37 05 04 F0 B7 3C 04 F0 13 05 05 14
23 A0 BC D4 EF F0 BF C5 37 05 04 F0 13 05 05 15
EF F0 FF C2 83 A5 8A D4 37 05 04 F0 13 05 85 18
B7 04 04 F0 EF F0 BF C3 95 45 13 85 44 1A EF F0
1F C3 83 25 CA E1 37 05 04 F0 13 05 05 1C EF F0
1F C2 85 45 13 85 44 1A EF F0 7F C1 83 C5 C9 D4
37 05 04 F0 13 05 C5 1D EF F0 7F C0 B7 09 04 F0
93 05 10 04 13 85 89 1F EF F0 7F BF 83 45 D4 D4
37 05 04 F0 13 05 45 21 EF F0 7F BE 93 05 20 04
13 85 89 1F EF F0 BF BD 93 8B 4B D5 83 A5 0B 02
37 05 04 F0 13 05 05 23 EF F0 7F BC 9D 45 13 85
44 1A EF F0 DF BB B7 07 04 F0 93 87 07 63 83 A5
C7 65 37 05 04 F0 13 05 C5 24 EF F0 5F BA 37 05
04 F0 13 05 85 26 EF F0 9F B7 03 27 0B D5 37 05
04 F0 13 05 45 29 0C 43 37 0C 04 F0 B7 0B 04 F0
EF F0 FF B7 37 05 04 F0 13 05 05 2B EF F0 3F B5
03 27 0B D5 13 05 0C 2E B7 0A 04 F0 4C 43 37 0A
04 F0 B7 09 04 F0 EF F0 9F B5 81 45 13 85 44 1A
EF F0 FF B4 03 27 0B D5 13 85 CB 2F 37 04 04 F0
0C 47 EF F0 DF B3 89 45 13 85 44 1A EF F0 3F B3
03 27 0B D5 13 85 8A 31 4C 47 EF F0 5F B2 C5 45
13 85 44 1A EF F0 BF B1 83 25 0B D5 13 05 4A 33
37 3B 04 F0 C1 05 EF F0 9F B0 13 85 C9 34 EF F0
1F AE 03 27 4B D4 37 05 04 F0 13 05 05 38 0C 43
EF F0 FF AE 37 05 04 F0 13 05 C5 39 EF F0 3F AC
03 27 4B D4 13 05 0C 2E 4C 43 EF F0 5F AD 81 45
13 85 44 1A EF F0 BF AC 03 27 4B D4 13 85 CB 2F
0C 47 EF F0 DF AB 85 45 13 85 44 1A EF F0 3F AB
03 27 4B D4 13 85 8A 31 4C 47 EF F0 5F AA C9 45
13 85 44 1A EF F0 BF A9 83 25 4B D4 13 05 4A 33
C1 05 EF F0 DF A8 13 85 C9 34 EF F0 5F A6 92 47
37 05 04 F0 13 05 C5 3D BE 85 EF F0 5F A7 95 45
13 85 44 1A EF F0 BF A6 B2 48 22 46 37 05 04 F0
33 09 19 41 93 17 39 00 33 89 27 41 B3 05 C9 40
13 05 85 3F EF F0 BF A4 B5 45 13 85 44 1A EF F0
1F A4 A2 55 37 05 04 F0 13 05 45 41 EF F0 3F A3
9D 45 13 85 44 1A EF F0 9F A2 B2 55 37 05 04 F0
13 05 05 43 EF F0 BF A1 85 45 13 85 44 1A EF F0
1F A1 37 05 04 F0 0C 18 13 05 C5 44 EF F0 3F A0
37 05 04 F0 13 05 45 46 EF F0 7F 9D 37 05 04 F0
8C 08 13 05 85 49 EF F0 9F 9E 37 05 04 F0 13 05
05 4B EF F0 DF 9B 29 45 EF F0 7F 99 B7 07 04 F0
03 A7 C7 62 83 A5 0C D4 93 07 70 0C 99 8D 23 24
B4 62 63 C9 B7 0A 37 05 04 F0 13 05 45 4E EF F0
1F 9B 37 05 04 F0 13 05 45 4F EF F0 5F 98 37 05
04 F0 13 05 C5 52 EF F0 9F 97 29 45 EF F0 3F 95
83 20 C1 10 03 24 81 10 83 24 41 10 03 29 01 10
FE 59 6E 5A DE 5A 4E 5B BE 5B 2E 5C 9E 5C 0E 5D
FE 4D 01 45 51 61 82 80 6C 10 01 45 EF F0 6F D8
03 AE 0C 00 03 A3 4C 00 83 A8 8C 00 03 A8 CC 00
03 A5 0C 01 83 A5 4C 01 03 A6 8C 01 83 D6 CC 01
03 C7 EC 01 83 47 D4 D4 05 0D F2 C8 9A CA C6 CC
C2 CE AA D0 AE D2 B2 D4 23 16 D1 06 23 07 E1 06
23 A4 9A D4 13 7D FD 0F 26 89 E3 F8 A7 C5 B5 B1
25 49 BD B1 37 05 04 F0 13 06 80 3E 13 05 C5 54
EF F0 FF 8F 37 05 04 F0 13 05 45 57 EF F0 3F 8F
83 25 84 62 B7 F7 76 48 93 87 07 80 B3 C7 B7 02
13 06 40 06 37 05 04 F0 13 05 45 59 33 E6 C7 02
B7 D7 9A 3B 93 87 07 A0 B3 C5 B7 02 EF F0 3F 8C
29 45 EF F0 DF 87 2D B7 37 05 04 F0 13 05 05 0E
EF F0 FF 88 FD B4
@F0040000
7E 03 00 EE BE 02 00 EE BE 02 00 EE BE 02 00 EE
BE 02 00 EE BE 02 00 EE BE 02 00 EE BE 02 00 EE
BE 02 00 EE BE 02 00 EE BE 02 00 EE C8 04 00 EE
70 04 00 EE BE 02 00 EE BE 02 00 EE BE 02 00 EE
BE 02 00 EE BE 02 00 EE BE 02 00 EE BE 02 00 EE
BE 02 00 EE BE 02 00 EE BE 02 00 EE 3A 04 00 EE
BE 02 00 EE BE 02 00 EE BE 02 00 EE 18 04 00 EE
BE 02 00 EE C4 03 00 EE BE 02 00 EE BE 02 00 EE
7E 03 00 EE 44 68 72 79 73 74 6F 6E 65 20 42 65
6E 63 68 6D 61 72 6B 2C 20 56 65 72 73 69 6F 6E
20 32 2E 31 20 28 4C 61 6E 67 75 61 67 65 3A 20
43 29 00 00 50 72 6F 67 72 61 6D 20 63 6F 6D 70
69 6C 65 64 20 77 69 74 68 20 27 72 65 67 69 73
74 65 72 27 20 61 74 74 72 69 62 75 74 65 00 00
50 72 6F 67 72 61 6D 20 63 6F 6D 70 69 6C 65 64
20 77 69 74 68 6F 75 74 20 27 72 65 67 69 73 74
65 72 27 20 61 74 74 72 69 62 75 74 65 00 00 00
45 78 65 63 75 74 69 6F 6E 20 73 74 61 72 74 73
2C 20 25 64 20 72 75 6E 73 20 74 68 72 6F 75 67
68 20 44 68 72 79 73 74 6F 6E 65 0A 00 00 00 00
45 6E 64 5F 74 69 6D 65 3D 25 64 0A 00 00 00 00
46 69 6E 61 6C 20 76 61 6C 75 65 73 20 6F 66 20
74 68 65 20 76 61 72 69 61 62 6C 65 73 20 75 73
65 64 20 69 6E 20 74 68 65 20 62 65 6E 63 68 6D
61 72 6B 3A 0A 00 00 00 49 6E 74 5F 47 6C 6F 62
3A 20 20 20 20 20 20 20 20 20 20 20 20 25 64 0A
00 00 00 00 20 20 20 20 20 20 20 20 73 68 6F 75
6C 64 20 62 65 3A 20 20 20 25 64 0A 00 00 00 00
42 6F 6F 6C 5F 47 6C 6F 62 3A 20 20 20 20 20 20
20 20 20 20 20 25 64 0A 00 00 00 00 43 68 5F 31
5F 47 6C 6F 62 3A 20 20 20 20 20 20 20 20 20 20
20 25 63 0A 00 00 00 00 20 20 20 20 20 20 20 20
73 68 6F 75 6C 64 20 62 65 3A 20 20 20 25 63 0A
00 00 00 00 43 68 5F 32 5F 47 6C 6F 62 3A 20 20
20 20 20 20 20 20 20 20 20 25 63 0A 00 00 00 00
41 72 72 5F 31 5F 47 6C 6F 62 5B 38 5D 3A 20 20
20 20 20 20 20 25 64 0A 00 00 00 00 41 72 72 5F
32 5F 47 6C 6F 62 5B 38 5D 5B 37 5D 3A 20 20 20
20 25 64 0A 00 00 00 00 20 20 20 20 20 20 20 20
73 68 6F 75 6C 64 20 62 65 3A 20 20 20 4E 75 6D
62 65 72 5F 4F 66 5F 52 75 6E 73 20 2B 20 31 30
00 00 00 00 50 74 72 5F 47 6C 6F 62 2D 3E 50 74
72 5F 43 6F 6D 70 3A 20 20 25 78 0A 00 00 00 00
20 20 20 20 20 20 20 20 73 68 6F 75 6C 64 20 62
65 3A 20 20 20 28 69 6D 70 6C 65 6D 65 6E 74 61
74 69 6F 6E 2D 64 65 70 65 6E 64 65 6E 74 29 00
20 20 44 69 73 63 72 3A 20 20 20 20 20 20 20 20
20 20 20 20 20 25 64 0A 00 00 00 00 20 20 45 6E
75 6D 5F 43 6F 6D 70 3A 20 20 20 20 20 20 20 20
20 25 64 0A 00 00 00 00 20 20 49 6E 74 5F 43 6F
6D 70 3A 20 20 20 20 20 20 20 20 20 20 25 64 0A
00 00 00 00 20 20 53 74 72 5F 43 6F 6D 70 3A 20
20 20 20 20 20 20 20 20 20 25 73 00 20 20 20 20
20 20 20 20 73 68 6F 75 6C 64 20 62 65 3A 20 20
20 44 48 52 59 53 54 4F 4E 45 20 50 52 4F 47 52
41 4D 2C 20 53 4F 4D 45 20 53 54 52 49 4E 47 00
4E 65 78 74 5F 50 74 72 5F 47 6C 6F 62 2D 3E 50
74 72 5F 43 6F 6D 70 3A 25 78 0A 00 20 20 20 20
20 20 20 20 73 68 6F 75 6C 64 20 62 65 3A 20 20
20 28 69 6D 70 6C 65 6D 65 6E 74 61 74 69 6F 6E
2D 64 65 70 65 6E 64 65 6E 74 29 2C 20 73 61 6D
65 20 61 73 20 61 62 6F 76 65 00 00 49 6E 74 5F
31 5F 4C 6F 63 3A 20 20 20 20 20 20 20 20 20 20
20 25 64 0A 00 00 00 00 49 6E 74 5F 32 5F 4C 6F
63 3A 20 20 20 20 20 20 20 20 20 20 20 25 64 0A
00 00 00 00 49 6E 74 5F 33 5F 4C 6F 63 3A 20 20
20 20 20 20 20 20 20 20 20 25 64 0A 00 00 00 00
45 6E 75 6D 5F 4C 6F 63 3A 20 20 20 20 20 20 20
20 20 20 20 20 25 64 0A 00 00 00 00 53 74 72 5F
31 5F 4C 6F 63 3A 20 20 20 20 20 20 20 20 20 20
20 25 73 00 20 20 20 20 20 20 20 20 73 68 6F 75
6C 64 20 62 65 3A 20 20 20 44 48 52 59 53 54 4F
4E 45 20 50 52 4F 47 52 41 4D 2C 20 31 27 53 54
20 53 54 52 49 4E 47 00 53 74 72 5F 32 5F 4C 6F
63 3A 20 20 20 20 20 20 20 20 20 20 20 25 73 00
20 20 20 20 20 20 20 20 73 68 6F 75 6C 64 20 62
65 3A 20 20 20 44 48 52 59 53 54 4F 4E 45 20 50
52 4F 47 52 41 4D 2C 20 32 27 4E 44 20 53 54 52
49 4E 47 00 55 73 65 72 20 74 69 6D 65 20 25 64
0A 00 00 00 4D 65 61 73 75 72 65 64 20 74 69 6D
65 20 74 6F 6F 20 73 6D 61 6C 6C 20 74 6F 20 6F
62 74 61 69 6E 20 6D 65 61 6E 69 6E 67 66 75 6C
20 72 65 73 75 6C 74 73 00 00 00 00 50 6C 65 61
73 65 20 69 6E 63 72 65 61 73 65 20 6E 75 6D 62
65 72 20 6F 66 20 72 75 6E 73 00 00 52 75 6E 20
74 69 6D 65 20 3D 20 25 64 20 63 6C 6F 63 6B 73
20 66 6F 72 20 25 64 20 44 68 72 79 73 74 6F 6E
65 73 0A 00 44 68 72 79 73 74 6F 6E 65 73 20 70
65 72 20 53 65 63 6F 6E 64 20 70 65 72 20 4D 48
7A 3A 20 00 25 64 2E 25 30 32 64 00 44 48 52 59
53 54 4F 4E 45 20 50 52 4F 47 52 41 4D 2C 20 53
4F 4D 45 20 53 54 52 49 4E 47 00 00 44 48 52 59
53 54 4F 4E 45 20 50 52 4F 47 52 41 4D 2C 20 31
27 53 54 20 53 54 52 49 4E 47 00 00 44 48 52 59
53 54 4F 4E 45 20 50 52 4F 47 52 41 4D 2C 20 32
27 4E 44 20 53 54 52 49 4E 47 00 00 44 48 52 59
53 54 4F 4E 45 20 50 52 4F 47 52 41 4D 2C 20 33
27 52 44 20 53 54 52 49 4E 47 00
@FFFFFFF0
00 00 00 EE FF FF 00 EE
@FFFFFFF8
00 00 04 F0 30 3E 04 F0

18
testbench/hex/program.hex
View File

@ -1,18 +0,0 @@
@00000000
73 10 20 B0 73 10 20 B8 B7 00 00 EE 73 90 50 30
B7 50 55 5F 93 80 50 55 73 90 00 7C B7 01 58 D0
17 12 00 00 13 02 02 FE 83 02 02 00 23 80 51 00
05 02 E3 9B 02 FE B7 01 58 D0 93 02 F0 0F 23 80
51 00 E3 0A 00 FE 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00
01 00 01 00 01 00 01 00 01 00 01 00 01 00

25
testbench/tb_top.sv
View File

@ -312,6 +312,7 @@ module tb_top ( input bit core_clk );
wire[63:0] WriteData; wire[63:0] WriteData;
string abi_reg[32]; // ABI register names string abi_reg[32]; // ABI register names
`define DEC rvtop.swerv.dec
assign mailbox_write = lmem.mailbox_write; assign mailbox_write = lmem.mailbox_write;
assign WriteData = lmem.WriteData; assign WriteData = lmem.WriteData;
@ -336,7 +337,7 @@ module tb_top ( input bit core_clk );
// End Of test monitor // End Of test monitor
if(mailbox_write && WriteData[7:0] == 8'hff) begin if(mailbox_write && WriteData[7:0] == 8'hff) begin
$display("TEST_PASSED"); $display("TEST_PASSED");
$display("\nFinished : minstret = %0d, mcycle = %0d", rvtop.swerv.dec.tlu.minstretl[31:0],rvtop.swerv.dec.tlu.mcyclel[31:0]); $display("\nFinished : minstret = %0d, mcycle = %0d", `DEC.tlu.minstretl[31:0],`DEC.tlu.mcyclel[31:0]);
$display("See \"exec.log\" for execution trace with register updates..\n"); $display("See \"exec.log\" for execution trace with register updates..\n");
$finish; $finish;
end end
@ -349,9 +350,9 @@ module tb_top ( input bit core_clk );
// trace monitor // trace monitor
always @(posedge core_clk) begin always @(posedge core_clk) begin
wb_valid <= rvtop.swerv.dec.dec_i0_wen_r; wb_valid <= `DEC.dec_i0_wen_r;
wb_dest <= rvtop.swerv.dec.dec_i0_waddr_r; wb_dest <= `DEC.dec_i0_waddr_r;
wb_data <= rvtop.swerv.dec.dec_i0_wdata_r; wb_data <= `DEC.dec_i0_wdata_r;
if (trace_rv_i_valid_ip) begin if (trace_rv_i_valid_ip) begin
$fwrite(tp,"%b,%h,%h,%0h,%0h,3,%b,%h,%h,%b\n", trace_rv_i_valid_ip, 0, trace_rv_i_address_ip, $fwrite(tp,"%b,%h,%h,%0h,%0h,3,%b,%h,%h,%b\n", trace_rv_i_valid_ip, 0, trace_rv_i_address_ip,
0, trace_rv_i_insn_ip,trace_rv_i_exception_ip,trace_rv_i_ecause_ip, 0, trace_rv_i_insn_ip,trace_rv_i_exception_ip,trace_rv_i_ecause_ip,
@ -365,10 +366,14 @@ module tb_top ( input bit core_clk );
dasm(trace_rv_i_insn_ip, trace_rv_i_address_ip, wb_dest & {5{wb_valid}}, wb_data) dasm(trace_rv_i_insn_ip, trace_rv_i_address_ip, wb_dest & {5{wb_valid}}, wb_data)
); );
end end
if(rvtop.swerv.dec.dec_nonblock_load_wen) if(`DEC.dec_nonblock_load_wen) begin
$fwrite (el, "%10d : %32s=%h ; nbL\n", cycleCnt, abi_reg[rvtop.swerv.dec.dec_nonblock_load_waddr], rvtop.swerv.dec.lsu_nonblock_load_data); $fwrite (el, "%10d : %32s=%h ; nbL\n", cycleCnt, abi_reg[`DEC.dec_nonblock_load_waddr], `DEC.lsu_nonblock_load_data);
if(rvtop.swerv.dec.exu_div_wren) tb_top.gpr[0][`DEC.dec_nonblock_load_waddr] = `DEC.lsu_nonblock_load_data;
$fwrite (el, "%10d : %32s=%h ; nbD\n", cycleCnt, abi_reg[rvtop.swerv.dec.div_waddr_wb], rvtop.swerv.dec.exu_div_result); end
if(`DEC.exu_div_wren) begin
$fwrite (el, "%10d : %32s=%h ; nbD\n", cycleCnt, abi_reg[`DEC.div_waddr_wb], `DEC.exu_div_result);
tb_top.gpr[0][`DEC.div_waddr_wb] = `DEC.exu_div_result;
end
end end
@ -952,7 +957,9 @@ addresses:
0xfffffff0 - ICCM start address to load 0xfffffff0 - ICCM start address to load
0xfffffff4 - ICCM end address to load 0xfffffff4 - ICCM end address to load
*/ */
`ifndef VERILATOR
init_iccm();
`endif
addr = 'hffff_fff0; addr = 'hffff_fff0;
saddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]}; saddr = {lmem.mem[addr+3],lmem.mem[addr+2],lmem.mem[addr+1],lmem.mem[addr]};
if ( (saddr < `RV_ICCM_SADR) || (saddr > `RV_ICCM_EADR)) return; if ( (saddr < `RV_ICCM_SADR) || (saddr > `RV_ICCM_EADR)) return;

14
testbench/tests/Coremark/Makefile
View File

@ -1,14 +0,0 @@
export TEST = cmark
#export CONF_PARAMS= -set=btb_size=512 -set=bht_size=2048 -set=iccm_size=128
export CONF_PARAMS= -set=btb_size=512 -set=bht_size=2048 -set=iccm_enable=0
export OFILES = crt0.o cmark.o printf.o
export BUILD_PATH = $(shell pwd)/snapshots/default
export TEST_CFLAGS = -finline-limit=400 -mbranch-cost=1 -Ofast -fno-code-hoisting -funroll-all-loops
program.hex:
$(MAKE) -e -f $(RV_ROOT)/tools/make.common $(BUILD_PATH)/defines.h
$(MAKE) -e -f $(RV_ROOT)/tools/make.common $@
.DEFAULT:
$(MAKE) -e program.hex
$(MAKE) -e -f $(RV_ROOT)/tools/make.common $@

2167
testbench/tests/Coremark/cmark.c
View File

File diff suppressed because it is too large Load Diff

262
testbench/tests/Coremark/printf.c
View File

@ -1,262 +0,0 @@
#include <stdarg.h>
#include "defines.h"
static int
whisperPutc(char c)
{
// __whisper_console_io = c;
// __whisper_console_io = c;
*(volatile char*)(RV_SERIALIO) = c;
return c;
}
static int
whisperPuts(const char* s)
{
while (*s)
whisperPutc(*s++);
return 1;
}
static int
whisperPrintUnsigned(unsigned value, int width, char pad)
{
char buffer[20];
int charCount = 0;
do
{
char c = '0' + (value % 10);
value = value / 10;
buffer[charCount++] = c;
}
while (value);
for (int i = charCount; i < width; ++i)
whisperPutc(pad);
char* p = buffer + charCount - 1;
for (int i = 0; i < charCount; ++i)
whisperPutc(*p--);
return charCount;
}
static int
whisperPrintDecimal(int value, int width, char pad)
{
char buffer[20];
int charCount = 0;
unsigned neg = value < 0;
if (neg)
{
value = -value;
whisperPutc('-');
width--;
}
do
{
char c = '0' + (value % 10);
value = value / 10;
buffer[charCount++] = c;
}
while (value);
for (int i = charCount; i < width; ++i)
whisperPutc(pad);
char* p = buffer + charCount - 1;
for (int i = 0; i < charCount; ++i)
whisperPutc(*p--);
if (neg)
charCount++;
return charCount;
}
static int
whisperPrintInt(int value, int width, int pad, int base)
{
if (base == 10)
return whisperPrintDecimal(value, width, pad);
char buffer[20];
int charCount = 0;
unsigned uu = value;
if (base == 8)
{
do
{
char c = '0' + (uu & 7);
buffer[charCount++] = c;
uu >>= 3;
}
while (uu);
}
else if (base == 16)
{
do
{
int digit = uu & 0xf;
char c = digit < 10 ? '0' + digit : 'a' + digit - 10;
buffer[charCount++] = c;
uu >>= 4;
}
while (uu);
}
else
return -1;
char* p = buffer + charCount - 1;
for (unsigned i = 0; i < charCount; ++i)
whisperPutc(*p--);
return charCount;
}
#if 0
// Print with g format
static int
whisperPrintDoubleG(double value)
{
return 0;
}
// Print with f format
static int
whisperPrintDoubleF(double value)
{
return 0;
}
#endif
int
whisperPrintfImpl(const char* format, va_list ap)
{
int count = 0; // Printed character count
for (const char* fp = format; *fp; fp++)
{
char pad = ' ';
int width = 0; // Field width
if (*fp != '%')
{
whisperPutc(*fp);
++count;
continue;
}
++fp; // Skip %
if (*fp == 0)
break;
if (*fp == '%')
{
whisperPutc('%');
continue;
}
while (*fp == '0')
{
pad = '0';
fp++; // Pad zero not yet implented.
}
if (*fp == '-')
{
fp++; // Pad right not yet implemented.
}
if (*fp == '*')
{
int outWidth = va_arg(ap, int);
fp++; // Width not yet implemented.
}
else if (*fp >= '0' && *fp <= '9')
{ // Width not yet implemented.
while (*fp >= '0' && *fp <= '9')
width = width * 10 + (*fp++ - '0');
}
switch (*fp)
{
case 'd':
count += whisperPrintDecimal(va_arg(ap, int), width, pad);
break;
case 'u':
count += whisperPrintUnsigned((unsigned) va_arg(ap, unsigned), width, pad);
break;
case 'x':
case 'X':
count += whisperPrintInt(va_arg(ap, int), width, pad, 16);
break;
case 'o':
count += whisperPrintInt(va_arg(ap, int), width, pad, 8);
break;
case 'c':
whisperPutc(va_arg(ap, int));
++count;
break;
case 's':
count += whisperPuts(va_arg(ap, char*));
break;
#if 0
case 'g':
count += whisperPrintDoubleG(va_arg(ap, double));
break;
case 'f':
count += whisperPrintDoubleF(va_arg(ap, double));
#endif
}
}
return count;
}
int
whisperPrintf(const char* format, ...)
{
va_list ap;
va_start(ap, format);
int code = whisperPrintfImpl(format, ap);
va_end(ap);
return code;
}
int
printf(const char* format, ...)
{
va_list ap;
va_start(ap, format);
int code = whisperPrintfImpl(format, ap);
va_end(ap);
return code;
}

24
testbench/tests/dhry/dhry_1.c
View File

@ -135,18 +135,14 @@ main ()
/* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */ /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */
/* overflow may occur for this array element. */ /* overflow may occur for this array element. */
printf ("\n");
printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
printf ("\n");
if (Reg) if (Reg)
{ {
printf ("Program compiled with 'register' attribute\n"); printf ("Program compiled with 'register' attribute\n");
printf ("\n");
} }
else else
{ {
printf ("Program compiled without 'register' attribute\n"); printf ("Program compiled without 'register' attribute\n");
printf ("\n");
} }
#ifndef SWERV #ifndef SWERV
@ -257,10 +253,7 @@ main ()
#endif #endif
printf ("Execution ends\n"); printf ("Final values of the variables used in the benchmark:\n\n");
printf ("\n");
printf ("Final values of the variables used in the benchmark:\n");
printf ("\n");
printf ("Int_Glob: %d\n", Int_Glob); printf ("Int_Glob: %d\n", Int_Glob);
printf (" should be: %d\n", 5); printf (" should be: %d\n", 5);
printf ("Bool_Glob: %d\n", Bool_Glob); printf ("Bool_Glob: %d\n", Bool_Glob);
@ -273,8 +266,7 @@ main ()
printf (" should be: %d\n", 7); printf (" should be: %d\n", 7);
printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]); printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]);
printf (" should be: Number_Of_Runs + 10\n"); printf (" should be: Number_Of_Runs + 10\n");
printf ("Ptr_Glob->\n"); printf ("Ptr_Glob->Ptr_Comp: %x\n", (int) Ptr_Glob->Ptr_Comp);
printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp);
printf (" should be: (implementation-dependent)\n"); printf (" should be: (implementation-dependent)\n");
printf (" Discr: %d\n", Ptr_Glob->Discr); printf (" Discr: %d\n", Ptr_Glob->Discr);
printf (" should be: %d\n", 0); printf (" should be: %d\n", 0);
@ -282,10 +274,9 @@ main ()
printf (" should be: %d\n", 2); printf (" should be: %d\n", 2);
printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp); printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp);
printf (" should be: %d\n", 17); printf (" should be: %d\n", 17);
printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp); printf (" Str_Comp: %s", Ptr_Glob->variant.var_1.Str_Comp);
printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n");
printf ("Next_Ptr_Glob->\n"); printf ("Next_Ptr_Glob->Ptr_Comp:%x\n", (int) Next_Ptr_Glob->Ptr_Comp);
printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp);
printf (" should be: (implementation-dependent), same as above\n"); printf (" should be: (implementation-dependent), same as above\n");
printf (" Discr: %d\n", Next_Ptr_Glob->Discr); printf (" Discr: %d\n", Next_Ptr_Glob->Discr);
printf (" should be: %d\n", 0); printf (" should be: %d\n", 0);
@ -293,8 +284,7 @@ main ()
printf (" should be: %d\n", 1); printf (" should be: %d\n", 1);
printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp); printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
printf (" should be: %d\n", 18); printf (" should be: %d\n", 18);
printf (" Str_Comp: %s\n", printf (" Str_Comp: %s", Next_Ptr_Glob->variant.var_1.Str_Comp);
Next_Ptr_Glob->variant.var_1.Str_Comp);
printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n");
printf ("Int_1_Loc: %d\n", Int_1_Loc); printf ("Int_1_Loc: %d\n", Int_1_Loc);
printf (" should be: %d\n", 5); printf (" should be: %d\n", 5);
@ -304,9 +294,9 @@ main ()
printf (" should be: %d\n", 7); printf (" should be: %d\n", 7);
printf ("Enum_Loc: %d\n", Enum_Loc); printf ("Enum_Loc: %d\n", Enum_Loc);
printf (" should be: %d\n", 1); printf (" should be: %d\n", 1);
printf ("Str_1_Loc: %s\n", Str_1_Loc); printf ("Str_1_Loc: %s", Str_1_Loc);
printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n"); printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n");
printf ("Str_2_Loc: %s\n", Str_2_Loc); printf ("Str_2_Loc: %s", Str_2_Loc);
printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n"); printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n");
printf ("\n"); printf ("\n");

6
testbench/tests/dhry/dhry_2.c
View File

@ -26,7 +26,7 @@
extern int Int_Glob; extern int Int_Glob;
extern char Ch_1_Glob; extern char Ch_1_Glob;
#if 0
int int
strcmp(const char* s1, const char* s2) strcmp(const char* s1, const char* s2)
{ {
@ -39,7 +39,9 @@ strcmp(const char* s1, const char* s2)
return 0; return 0;
return *s1 > *s2? 1 : -1; return *s1 > *s2? 1 : -1;
} }
#else
extern int strcmp( char* s1, char* s2);
#endif
Boolean Func_3 (Enumeration Enum_Par_Val); Boolean Func_3 (Enumeration Enum_Par_Val);

19
tools/Makefile
View File

@ -41,22 +41,13 @@ TBDIR = ${RV_ROOT}/testbench
# Define test name # Define test name
TEST = hello_world TEST = hello_world
TEST_DIR = ${TBDIR}/asm
HEX_DIR = ${TBDIR}/hex
# Define test name # Determine test directory
ifneq (,$(wildcard $(TBDIR)/asm/$(TEST).s))
TEST_DIR = ${TBDIR}/asm
else
ifneq (,$(wildcard $(TBDIR)/asm/$(TEST).c))
TEST_DIR = ${TBDIR}/asm
else
ifneq (,$(wildcard $(TBDIR)/tests/$(TEST))) ifneq (,$(wildcard $(TBDIR)/tests/$(TEST)))
TEST_DIR = $(TBDIR)/tests/$(TEST) TEST_DIR = $(TBDIR)/tests/$(TEST)
else
TEST_DIR = ${TBDIR}/asm
endif endif
endif
endif
HEX_DIR = ${TBDIR}/hex
OFILES = $(TEST).o OFILES = $(TEST).o
@ -101,7 +92,7 @@ VERILATOR_MAKE_FLAGS = OPT_FAST="-Os"
all: clean verilator all: clean verilator
clean: clean:
rm -rf *.log *.s *.hex *.dis *.tbl irun* vcs* simv* snapshots swerv* \ rm -rf *.log *.s *.hex *.dis *.tbl irun* vcs* simv* *.map snapshots swerv* \
verilator* *.exe obj* *.o ucli.key vc_hdrs.h csrc *.csv work\ verilator* *.exe obj* *.o ucli.key vc_hdrs.h csrc *.csv work\
dataset.asdb library.cfg vsimsa.cfg riviera-build wave.asdb dataset.asdb library.cfg vsimsa.cfg riviera-build wave.asdb
@ -189,7 +180,7 @@ program.hex:
else else
program.hex: $(OFILES) $(LINK) program.hex: $(OFILES) $(LINK)
@echo Building $(TEST) @echo Building $(TEST)
$(GCC_PREFIX)-gcc -Wl,-m,elf32lriscv -Wl,--discard-none -T$(LINK) -o $(TEST).exe $(OFILES) -nostartfiles -nostdlib $(TEST_LIBS) $(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(TEST).map -lgcc -T$(LINK) -o $(TEST).exe $(OFILES) -nostartfiles $(TEST_LIBS)
$(GCC_PREFIX)-objcopy -O verilog $(TEST).exe program.hex $(GCC_PREFIX)-objcopy -O verilog $(TEST).exe program.hex
$(GCC_PREFIX)-objdump -S $(TEST).exe > $(TEST).dis $(GCC_PREFIX)-objdump -S $(TEST).exe > $(TEST).dis
@echo Completed building $(TEST) @echo Completed building $(TEST)