165 lines
6.6 KiB
Systemverilog
165 lines
6.6 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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module el2_dec_ib_ctl
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import el2_pkg::*;
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#(
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`include "el2_param.vh"
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)
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(
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input logic dbg_cmd_valid, // valid dbg cmd
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input logic dbg_cmd_write, // dbg cmd is write
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input logic [1:0] dbg_cmd_type, // dbg type
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input logic [31:0] dbg_cmd_addr, // expand to 31:0
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input el2_br_pkt_t i0_brp, // i0 branch packet from aligner
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input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
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input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
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input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
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input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index
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input logic ifu_i0_pc4, // i0 is 4B inst else 2B
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input logic ifu_i0_valid, // i0 valid from ifu
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input logic ifu_i0_icaf, // i0 instruction access fault
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input logic [1:0] ifu_i0_icaf_type, // i0 instruction access fault type
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input logic ifu_i0_icaf_second, // i0 has access fault on second 2B of 4B inst
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input logic ifu_i0_dbecc, // i0 double-bit error
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input logic [31:0] ifu_i0_instr, // i0 instruction from the aligner
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input logic [31:1] ifu_i0_pc, // i0 pc from the aligner
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output logic dec_ib0_valid_d, // ib0 valid
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output logic dec_debug_valid_d, // Debug read or write at D-stage
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output logic [31:0] dec_i0_instr_d, // i0 inst at decode
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output logic [31:1] dec_i0_pc_d, // i0 pc at decode
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output logic dec_i0_pc4_d, // i0 is 4B inst else 2B
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output el2_br_pkt_t dec_i0_brp, // i0 branch packet at decode
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output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index, // i0 branch index
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output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr, // BP FGHR
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output logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag
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output logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index, // Fully associt btb index
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output logic dec_i0_icaf_d, // i0 instruction access fault at decode
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output logic dec_i0_icaf_second_d, // i0 instruction access fault on second 2B of 4B inst
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output logic [1:0] dec_i0_icaf_type_d, // i0 instruction access fault type
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output logic dec_i0_dbecc_d, // i0 double-bit error at decode
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output logic dec_debug_wdata_rs1_d, // put debug write data onto rs1 source: machine is halted
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output logic dec_debug_fence_d // debug fence inst
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);
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logic debug_valid;
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logic [4:0] dreg;
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logic [11:0] dcsr;
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logic [31:0] ib0, ib0_debug_in;
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logic debug_read;
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logic debug_write;
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logic debug_read_gpr;
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logic debug_write_gpr;
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logic debug_read_csr;
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logic debug_write_csr;
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logic [34:0] ifu_i0_pcdata, pc0;
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assign ifu_i0_pcdata[34:0] = { ifu_i0_icaf_second, ifu_i0_dbecc, ifu_i0_icaf,
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ifu_i0_pc[31:1], ifu_i0_pc4 };
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assign pc0[34:0] = ifu_i0_pcdata[34:0];
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assign dec_i0_icaf_second_d = pc0[34]; // icaf's can only decode as i0
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assign dec_i0_dbecc_d = pc0[33];
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assign dec_i0_icaf_d = pc0[32];
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assign dec_i0_pc_d[31:1] = pc0[31:1];
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assign dec_i0_pc4_d = pc0[0];
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assign dec_i0_icaf_type_d[1:0] = ifu_i0_icaf_type[1:0];
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// GPR accesses
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// put reg to read on rs1
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// read -> or %x0, %reg,%x0 {000000000000,reg[4:0],110000000110011}
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// put write date on rs1
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// write -> or %reg, %x0, %x0 {00000000000000000110,reg[4:0],0110011}
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// CSR accesses
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// csr is of form rd, csr, rs1
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// read -> csrrs %x0, %csr, %x0 {csr[11:0],00000010000001110011}
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// put write data on rs1
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// write -> csrrw %x0, %csr, %x0 {csr[11:0],00000001000001110011}
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// abstract memory command not done here
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assign debug_valid = dbg_cmd_valid & (dbg_cmd_type[1:0] != 2'h2);
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assign debug_read = debug_valid & ~dbg_cmd_write;
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assign debug_write = debug_valid & dbg_cmd_write;
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assign debug_read_gpr = debug_read & (dbg_cmd_type[1:0]==2'h0);
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assign debug_write_gpr = debug_write & (dbg_cmd_type[1:0]==2'h0);
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assign debug_read_csr = debug_read & (dbg_cmd_type[1:0]==2'h1);
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assign debug_write_csr = debug_write & (dbg_cmd_type[1:0]==2'h1);
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assign dreg[4:0] = dbg_cmd_addr[4:0];
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assign dcsr[11:0] = dbg_cmd_addr[11:0];
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assign ib0_debug_in[31:0] = ({32{debug_read_gpr}} & {12'b000000000000,dreg[4:0],15'b110000000110011}) |
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({32{debug_write_gpr}} & {20'b00000000000000000110,dreg[4:0],7'b0110011}) |
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({32{debug_read_csr}} & {dcsr[11:0],20'b00000010000001110011}) |
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({32{debug_write_csr}} & {dcsr[11:0],20'b00000001000001110011});
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// machine is in halted state, pipe empty, write will always happen next cycle
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assign dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr;
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// special fence csr for use only in debug mode
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assign dec_debug_fence_d = debug_write_csr & (dcsr[11:0] == 12'h7c4);
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assign ib0[31:0] = (debug_valid) ? ib0_debug_in[31:0] : ifu_i0_instr[31:0];
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assign dec_ib0_valid_d = ifu_i0_valid | debug_valid;
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assign dec_debug_valid_d = debug_valid;
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assign dec_i0_instr_d[31:0] = ib0[31:0];
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assign dec_i0_brp = i0_brp;
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assign dec_i0_bp_index = ifu_i0_bp_index;
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assign dec_i0_bp_fghr = ifu_i0_bp_fghr;
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assign dec_i0_bp_btag = ifu_i0_bp_btag;
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assign dec_i0_bp_fa_index = ifu_i0_fa_index;
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endmodule
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