370 lines
20 KiB
Systemverilog
370 lines
20 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or it's affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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//
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// Owner:
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// Function: lsu interface with interface queue
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// Comments:
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//
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//********************************************************************************
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module el2_lsu_bus_intf
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import el2_pkg::*;
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#(
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`include "el2_param.vh"
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)(
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input logic clk,
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input logic rst_l,
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input logic scan_mode,
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input logic dec_tlu_external_ldfwd_disable, // disable load to load forwarding for externals
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input logic dec_tlu_wb_coalescing_disable, // disable write buffer coalescing
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input logic dec_tlu_sideeffect_posted_disable, // disable the posted sideeffect load store to the bus
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// various clocks needed for the bus reads and writes
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input logic lsu_c1_m_clk,
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input logic lsu_c1_r_clk,
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input logic lsu_c2_r_clk,
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input logic lsu_bus_ibuf_c1_clk,
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input logic lsu_bus_obuf_c1_clk,
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input logic lsu_bus_buf_c1_clk,
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input logic lsu_free_c2_clk,
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input logic free_clk,
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input logic lsu_busm_clk,
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input logic dec_lsu_valid_raw_d, // Raw valid for address computation
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input logic lsu_busreq_m, // bus request is in m
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input el2_lsu_pkt_t lsu_pkt_m, // lsu packet flowing down the pipe
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input el2_lsu_pkt_t lsu_pkt_r, // lsu packet flowing down the pipe
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input logic [31:0] lsu_addr_d, // lsu address flowing down the pipe
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input logic [31:0] lsu_addr_m, // lsu address flowing down the pipe
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input logic [31:0] lsu_addr_r, // lsu address flowing down the pipe
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input logic [31:0] end_addr_d, // lsu address flowing down the pipe
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input logic [31:0] end_addr_m, // lsu address flowing down the pipe
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input logic [31:0] end_addr_r, // lsu address flowing down the pipe
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input logic [31:0] store_data_r, // store data flowing down the pipe
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input logic dec_tlu_force_halt,
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input logic lsu_commit_r, // lsu instruction in r commits
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input logic is_sideeffects_m, // lsu attribute is side_effects
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input logic flush_m_up, // flush
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input logic flush_r, // flush
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output logic lsu_busreq_r, // bus request is in r
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output logic lsu_bus_buffer_pend_any, // bus buffer has a pending bus entry
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output logic lsu_bus_buffer_full_any, // write buffer is full
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output logic lsu_bus_buffer_empty_any, // write buffer is empty
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output logic lsu_bus_idle_any, // NO pending responses from the bus
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output logic [31:0] bus_read_data_m, // the bus return data
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output logic lsu_imprecise_error_load_any, // imprecise load bus error
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output logic lsu_imprecise_error_store_any, // imprecise store bus error
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output logic [31:0] lsu_imprecise_error_addr_any, // address of the imprecise error
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// Non-blocking loads
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output logic lsu_nonblock_load_valid_m, // there is an external load -> put in the cam
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output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // the tag of the external non block load
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output logic lsu_nonblock_load_inv_r, // invalidate signal for the cam entry for non block loads
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output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated
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output logic lsu_nonblock_load_data_valid,// the non block is valid - sending information back to the cam
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output logic lsu_nonblock_load_data_error,// non block load has an error
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output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // the tag of the non block load sending the data/error
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output logic [31:0] lsu_nonblock_load_data, // Data of the non block load
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// PMU events
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output logic lsu_pmu_bus_trxn,
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output logic lsu_pmu_bus_misaligned,
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output logic lsu_pmu_bus_error,
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output logic lsu_pmu_bus_busy,
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// AXI Write Channels
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output logic lsu_axi_awvalid,
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input logic lsu_axi_awready,
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output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
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output logic [31:0] lsu_axi_awaddr,
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output logic [3:0] lsu_axi_awregion,
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output logic [7:0] lsu_axi_awlen,
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output logic [2:0] lsu_axi_awsize,
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output logic [1:0] lsu_axi_awburst,
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output logic lsu_axi_awlock,
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output logic [3:0] lsu_axi_awcache,
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output logic [2:0] lsu_axi_awprot,
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output logic [3:0] lsu_axi_awqos,
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output logic lsu_axi_wvalid,
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input logic lsu_axi_wready,
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output logic [63:0] lsu_axi_wdata,
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output logic [7:0] lsu_axi_wstrb,
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output logic lsu_axi_wlast,
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input logic lsu_axi_bvalid,
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output logic lsu_axi_bready,
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input logic [1:0] lsu_axi_bresp,
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input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
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// AXI Read Channels
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output logic lsu_axi_arvalid,
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input logic lsu_axi_arready,
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output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
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output logic [31:0] lsu_axi_araddr,
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output logic [3:0] lsu_axi_arregion,
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output logic [7:0] lsu_axi_arlen,
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output logic [2:0] lsu_axi_arsize,
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output logic [1:0] lsu_axi_arburst,
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output logic lsu_axi_arlock,
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output logic [3:0] lsu_axi_arcache,
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output logic [2:0] lsu_axi_arprot,
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output logic [3:0] lsu_axi_arqos,
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input logic lsu_axi_rvalid,
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output logic lsu_axi_rready,
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input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
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input logic [63:0] lsu_axi_rdata,
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input logic [1:0] lsu_axi_rresp,
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input logic lsu_axi_rlast,
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input logic lsu_bus_clk_en
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);
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logic lsu_bus_clk_en_q;
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logic ldst_dual_d, ldst_dual_m, ldst_dual_r;
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logic [3:0] ldst_byteen_m, ldst_byteen_r;
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logic [7:0] ldst_byteen_ext_m, ldst_byteen_ext_r;
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logic [3:0] ldst_byteen_hi_m, ldst_byteen_hi_r;
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logic [3:0] ldst_byteen_lo_m, ldst_byteen_lo_r;
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logic is_sideeffects_r;
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logic [63:0] store_data_ext_r;
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logic [31:0] store_data_hi_r;
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logic [31:0] store_data_lo_r;
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logic addr_match_dw_lo_r_m;
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logic addr_match_word_lo_r_m;
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logic no_word_merge_r, no_dword_merge_r;
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logic ld_addr_rhit_lo_lo, ld_addr_rhit_hi_lo, ld_addr_rhit_lo_hi, ld_addr_rhit_hi_hi;
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logic [3:0] ld_byte_rhit_lo_lo, ld_byte_rhit_hi_lo, ld_byte_rhit_lo_hi, ld_byte_rhit_hi_hi;
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logic [3:0] ld_byte_hit_lo, ld_byte_rhit_lo;
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logic [3:0] ld_byte_hit_hi, ld_byte_rhit_hi;
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logic [31:0] ld_fwddata_rpipe_lo;
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logic [31:0] ld_fwddata_rpipe_hi;
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logic [3:0] ld_byte_hit_buf_lo, ld_byte_hit_buf_hi;
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logic [31:0] ld_fwddata_buf_lo, ld_fwddata_buf_hi;
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logic [63:0] ld_fwddata_lo, ld_fwddata_hi;
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logic [63:0] ld_fwddata_m;
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logic ld_full_hit_hi_m, ld_full_hit_lo_m;
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logic ld_full_hit_m;
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assign ldst_byteen_m[3:0] = ({4{lsu_pkt_m.by}} & 4'b0001) |
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({4{lsu_pkt_m.half}} & 4'b0011) |
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({4{lsu_pkt_m.word}} & 4'b1111);
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assign ldst_dual_d = (lsu_addr_d[2] != end_addr_d[2]);
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// Read/Write Buffer
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el2_lsu_bus_buffer #(.pt(pt)) bus_buffer (
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.*
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);
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// Logic to determine if dc5 store can be coalesced or not with younger stores. Bypass ibuf if cannot colaesced
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assign addr_match_dw_lo_r_m = (lsu_addr_r[31:3] == lsu_addr_m[31:3]);
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assign addr_match_word_lo_r_m = addr_match_dw_lo_r_m & ~(lsu_addr_r[2]^lsu_addr_m[2]);
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assign no_word_merge_r = lsu_busreq_r & ~ldst_dual_r & lsu_busreq_m & (lsu_pkt_m.load | ~addr_match_word_lo_r_m);
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assign no_dword_merge_r = lsu_busreq_r & ~ldst_dual_r & lsu_busreq_m & (lsu_pkt_m.load | ~addr_match_dw_lo_r_m);
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// Create Hi/Lo signals
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assign ldst_byteen_ext_m[7:0] = {4'b0,ldst_byteen_m[3:0]} << lsu_addr_m[1:0];
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assign ldst_byteen_ext_r[7:0] = {4'b0,ldst_byteen_r[3:0]} << lsu_addr_r[1:0];
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assign store_data_ext_r[63:0] = {32'b0,store_data_r[31:0]} << {lsu_addr_r[1:0],3'b0};
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assign ldst_byteen_hi_m[3:0] = ldst_byteen_ext_m[7:4];
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assign ldst_byteen_lo_m[3:0] = ldst_byteen_ext_m[3:0];
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assign ldst_byteen_hi_r[3:0] = ldst_byteen_ext_r[7:4];
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assign ldst_byteen_lo_r[3:0] = ldst_byteen_ext_r[3:0];
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assign store_data_hi_r[31:0] = store_data_ext_r[63:32];
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assign store_data_lo_r[31:0] = store_data_ext_r[31:0];
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assign ld_addr_rhit_lo_lo = (lsu_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m;
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assign ld_addr_rhit_lo_hi = (end_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m;
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assign ld_addr_rhit_hi_lo = (lsu_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m;
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assign ld_addr_rhit_hi_hi = (end_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m;
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for (genvar i=0; i<4; i++) begin: GenBusBufFwd
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assign ld_byte_rhit_lo_lo[i] = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[i] & ldst_byteen_lo_m[i];
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assign ld_byte_rhit_lo_hi[i] = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[i] & ldst_byteen_hi_m[i];
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assign ld_byte_rhit_hi_lo[i] = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[i] & ldst_byteen_lo_m[i];
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assign ld_byte_rhit_hi_hi[i] = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[i] & ldst_byteen_hi_m[i];
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assign ld_byte_hit_lo[i] = ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i] |
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ld_byte_hit_buf_lo[i];
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assign ld_byte_hit_hi[i] = ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i] |
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ld_byte_hit_buf_hi[i];
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assign ld_byte_rhit_lo[i] = ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i];
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assign ld_byte_rhit_hi[i] = ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i];
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assign ld_fwddata_rpipe_lo[(8*i)+7:(8*i)] = ({8{ld_byte_rhit_lo_lo[i]}} & store_data_lo_r[(8*i)+7:(8*i)]) |
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({8{ld_byte_rhit_hi_lo[i]}} & store_data_hi_r[(8*i)+7:(8*i)]);
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assign ld_fwddata_rpipe_hi[(8*i)+7:(8*i)] = ({8{ld_byte_rhit_lo_hi[i]}} & store_data_lo_r[(8*i)+7:(8*i)]) |
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({8{ld_byte_rhit_hi_hi[i]}} & store_data_hi_r[(8*i)+7:(8*i)]);
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// Final muxing between m/r
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assign ld_fwddata_lo[(8*i)+7:(8*i)] = ld_byte_rhit_lo[i] ? ld_fwddata_rpipe_lo[(8*i)+7:(8*i)] : ld_fwddata_buf_lo[(8*i)+7:(8*i)];
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assign ld_fwddata_hi[(8*i)+7:(8*i)] = ld_byte_rhit_hi[i] ? ld_fwddata_rpipe_hi[(8*i)+7:(8*i)] : ld_fwddata_buf_hi[(8*i)+7:(8*i)];
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end
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always_comb begin
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ld_full_hit_lo_m = 1'b1;
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ld_full_hit_hi_m = 1'b1;
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for (int i=0; i<4; i++) begin
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ld_full_hit_lo_m &= (ld_byte_hit_lo[i] | ~ldst_byteen_lo_m[i]);
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ld_full_hit_hi_m &= (ld_byte_hit_hi[i] | ~ldst_byteen_hi_m[i]);
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end
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end
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// This will be high if all the bytes of load hit the stores in pipe/write buffer (m/r/wrbuf)
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assign ld_full_hit_m = ld_full_hit_lo_m & ld_full_hit_hi_m & lsu_busreq_m & lsu_pkt_m.load & ~is_sideeffects_m;
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assign ld_fwddata_m[63:0] = {ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8*lsu_addr_m[1:0]);
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assign bus_read_data_m[31:0] = ld_fwddata_m[31:0];
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// Fifo flops
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rvdff #(.WIDTH(1)) clken_ff (.din(lsu_bus_clk_en), .dout(lsu_bus_clk_en_q), .clk(free_clk), .*);
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rvdff #(.WIDTH(1)) ldst_dual_mff (.din(ldst_dual_d), .dout(ldst_dual_m), .clk(lsu_c1_m_clk), .*);
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rvdff #(.WIDTH(1)) ldst_dual_rff (.din(ldst_dual_m), .dout(ldst_dual_r), .clk(lsu_c1_r_clk), .*);
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rvdff #(.WIDTH(1)) is_sideeffects_rff (.din(is_sideeffects_m), .dout(is_sideeffects_r), .clk(lsu_c1_r_clk), .*);
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rvdff #(4) lsu_byten_rff (.*, .din(ldst_byteen_m[3:0]), .dout(ldst_byteen_r[3:0]), .clk(lsu_c1_r_clk));
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`ifdef ASSERT_ON
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// Assertion to check AXI write address is aligned to size
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property lsu_axi_awaddr_aligned;
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@(posedge lsu_busm_clk) disable iff(~rst_l) lsu_axi_awvalid |-> ((lsu_axi_awsize[2:0] == 3'h0) |
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((lsu_axi_awsize[2:0] == 3'h1) & (lsu_axi_awaddr[0] == 1'b0)) |
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((lsu_axi_awsize[2:0] == 3'h2) & (lsu_axi_awaddr[1:0] == 2'b0)) |
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((lsu_axi_awsize[2:0] == 3'h3) & (lsu_axi_awaddr[2:0] == 3'b0)));
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endproperty
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assert_lsu_axi_awaddr_aligned: assert property (lsu_axi_awaddr_aligned) else
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$display("Assertion lsu_axi_awaddr_aligned failed: lsu_axi_awvalid=1'b%b, lsu_axi_awsize=3'h%h, lsu_axi_awaddr=32'h%h",lsu_axi_awvalid, lsu_axi_awsize[2:0], lsu_axi_awaddr[31:0]);
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// Assertion to check awvalid stays stable during entire bus clock
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// Assertion to check AXI read address is aligned to size
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property lsu_axi_araddr_aligned;
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@(posedge lsu_busm_clk) disable iff(~rst_l) lsu_axi_arvalid |-> ((lsu_axi_arsize[2:0] == 3'h0) |
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((lsu_axi_arsize[2:0] == 3'h1) & (lsu_axi_araddr[0] == 1'b0)) |
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((lsu_axi_arsize[2:0] == 3'h2) & (lsu_axi_araddr[1:0] == 2'b0)) |
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((lsu_axi_arsize[2:0] == 3'h3) & (lsu_axi_araddr[2:0] == 3'b0)));
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endproperty
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assert_lsu_axi_araddr_aligned: assert property (lsu_axi_araddr_aligned) else
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$display("Assertion lsu_axi_araddr_aligned failed: lsu_axi_awvalid=1'b%b, lsu_axi_awsize=3'h%h, lsu_axi_araddr=32'h%h",lsu_axi_awvalid, lsu_axi_awsize[2:0], lsu_axi_araddr[31:0]);
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// Assertion to check awvalid stays stable during entire bus clock
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property lsu_axi_awvalid_stable;
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@(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid != $past(lsu_axi_awvalid)) |-> $past(lsu_bus_clk_en);
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endproperty
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assert_lsu_axi_awvalid_stable: assert property (lsu_axi_awvalid_stable) else
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$display("LSU AXI awvalid changed in middle of bus clock");
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// Assertion to check awid stays stable during entire bus clock
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property lsu_axi_awid_stable;
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@(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_awid[pt.LSU_BUS_TAG-1:0] != $past(lsu_axi_awid[pt.LSU_BUS_TAG-1:0]))) |-> $past(lsu_bus_clk_en);
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endproperty
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assert_lsu_axi_awid_stable: assert property (lsu_axi_awid_stable) else
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$display("LSU AXI awid changed in middle of bus clock");
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// Assertion to check awaddr stays stable during entire bus clock
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property lsu_axi_awaddr_stable;
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@(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_awaddr[31:0] != $past(lsu_axi_awaddr[31:0]))) |-> $past(lsu_bus_clk_en);
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endproperty
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assert_lsu_axi_awaddr_stable: assert property (lsu_axi_awaddr_stable) else
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$display("LSU AXI awaddr changed in middle of bus clock");
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// Assertion to check awsize stays stable during entire bus clock
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property lsu_axi_awsize_stable;
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@(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_awsize[2:0] != $past(lsu_axi_awsize[2:0]))) |-> $past(lsu_bus_clk_en);
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endproperty
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assert_lsu_axi_awsize_stable: assert property (lsu_axi_awsize_stable) else
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$display("LSU AXI awsize changed in middle of bus clock");
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// Assertion to check wstrb stays stable during entire bus clock
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property lsu_axi_wstrb_stable;
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@(posedge clk) disable iff(~rst_l) (lsu_axi_wvalid & (lsu_axi_wstrb[7:0] != $past(lsu_axi_wstrb[7:0]))) |-> $past(lsu_bus_clk_en);
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endproperty
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assert_lsu_axi_wstrb_stable: assert property (lsu_axi_wstrb_stable) else
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$display("LSU AXI wstrb changed in middle of bus clock");
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// Assertion to check wdata stays stable during entire bus clock
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property lsu_axi_wdata_stable;
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@(posedge clk) disable iff(~rst_l) (lsu_axi_wvalid & (lsu_axi_wdata[63:0] != $past(lsu_axi_wdata[63:0]))) |-> $past(lsu_bus_clk_en);
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endproperty
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assert_lsu_axi_wdata_stable: assert property (lsu_axi_wdata_stable) else
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$display("LSU AXI wdata changed in middle of bus clock");
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// Assertion to check awvalid stays stable during entire bus clock
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property lsu_axi_arvalid_stable;
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@(posedge clk) disable iff(~rst_l) (lsu_axi_arvalid != $past(lsu_axi_arvalid)) |-> $past(lsu_bus_clk_en);
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endproperty
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assert_lsu_axi_arvalid_stable: assert property (lsu_axi_arvalid_stable) else
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$display("LSU AXI awvalid changed in middle of bus clock");
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// Assertion to check awid stays stable during entire bus clock
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property lsu_axi_arid_stable;
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@(posedge clk) disable iff(~rst_l) (lsu_axi_arvalid & (lsu_axi_arid[pt.LSU_BUS_TAG-1:0] != $past(lsu_axi_arid[pt.LSU_BUS_TAG-1:0]))) |-> $past(lsu_bus_clk_en);
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endproperty
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assert_lsu_axi_arid_stable: assert property (lsu_axi_arid_stable) else
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$display("LSU AXI awid changed in middle of bus clock");
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// Assertion to check awaddr stays stable during entire bus clock
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property lsu_axi_araddr_stable;
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@(posedge clk) disable iff(~rst_l) (lsu_axi_arvalid & (lsu_axi_araddr[31:0] != $past(lsu_axi_araddr[31:0]))) |-> $past(lsu_bus_clk_en);
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endproperty
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assert_lsu_axi_araddr_stable: assert property (lsu_axi_araddr_stable) else
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$display("LSU AXI awaddr changed in middle of bus clock");
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// Assertion to check awsize stays stable during entire bus clock
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property lsu_axi_arsize_stable;
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@(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_arsize[2:0] != $past(lsu_axi_arsize[2:0]))) |-> $past(lsu_bus_clk_en);
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endproperty
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assert_lsu_axi_arsize_stable: assert property (lsu_axi_arsize_stable) else
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$display("LSU AXI awsize changed in middle of bus clock");
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`endif
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endmodule // el2_lsu_bus_intf
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