478 lines
25 KiB
Systemverilog
478 lines
25 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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// Owner:
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// Function: AXI4 -> AHB Bridge
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// Comments:
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//
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//********************************************************************************
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module axi4_to_ahb
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import el2_pkg::*;
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#(
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`include "el2_param.vh"
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,parameter TAG = 1) (
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input clk,
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input free_clk,
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input rst_l,
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input scan_mode,
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input bus_clk_en,
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input clk_override,
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input dec_tlu_force_halt,
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// AXI signals
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// AXI Write Channels
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input logic axi_awvalid,
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output logic axi_awready,
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input logic [TAG-1:0] axi_awid,
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input logic [31:0] axi_awaddr,
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input logic [2:0] axi_awsize,
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input logic [2:0] axi_awprot,
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input logic axi_wvalid,
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output logic axi_wready,
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input logic [63:0] axi_wdata,
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input logic [7:0] axi_wstrb,
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input logic axi_wlast,
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output logic axi_bvalid,
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input logic axi_bready,
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output logic [1:0] axi_bresp,
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output logic [TAG-1:0] axi_bid,
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// AXI Read Channels
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input logic axi_arvalid,
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output logic axi_arready,
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input logic [TAG-1:0] axi_arid,
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input logic [31:0] axi_araddr,
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input logic [2:0] axi_arsize,
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input logic [2:0] axi_arprot,
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output logic axi_rvalid,
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input logic axi_rready,
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output logic [TAG-1:0] axi_rid,
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output logic [63:0] axi_rdata,
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output logic [1:0] axi_rresp,
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output logic axi_rlast,
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// AHB-Lite signals
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output logic [31:0] ahb_haddr, // ahb bus address
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output logic [2:0] ahb_hburst, // tied to 0
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output logic ahb_hmastlock, // tied to 0
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output logic [3:0] ahb_hprot, // tied to 4'b0011
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output logic [2:0] ahb_hsize, // size of bus transaction (possible values 0,1,2,3)
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output logic [1:0] ahb_htrans, // Transaction type (possible values 0,2 only right now)
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output logic ahb_hwrite, // ahb bus write
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output logic [63:0] ahb_hwdata, // ahb bus write data
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input logic [63:0] ahb_hrdata, // ahb bus read data
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input logic ahb_hready, // slave ready to accept transaction
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input logic ahb_hresp // slave response (high indicates erro)
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);
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localparam ID = 1;
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localparam PRTY = 1;
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typedef enum logic [2:0] {IDLE=3'b000, CMD_RD=3'b001, CMD_WR=3'b010, DATA_RD=3'b011, DATA_WR=3'b100, DONE=3'b101, STREAM_RD=3'b110, STREAM_ERR_RD=3'b111} state_t;
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state_t buf_state, buf_nxtstate;
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logic slave_valid;
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logic slave_ready;
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logic [TAG-1:0] slave_tag;
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logic [63:0] slave_rdata;
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logic [3:0] slave_opc;
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logic wrbuf_en, wrbuf_data_en;
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logic wrbuf_cmd_sent, wrbuf_rst;
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logic wrbuf_vld;
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logic wrbuf_data_vld;
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logic [TAG-1:0] wrbuf_tag;
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logic [2:0] wrbuf_size;
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logic [31:0] wrbuf_addr;
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logic [63:0] wrbuf_data;
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logic [7:0] wrbuf_byteen;
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logic master_valid;
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logic master_ready;
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logic [TAG-1:0] master_tag;
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logic [31:0] master_addr;
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logic [63:0] master_wdata;
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logic [2:0] master_size;
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logic [2:0] master_opc;
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logic [7:0] master_byteen;
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// Buffer signals (one entry buffer)
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logic [31:0] buf_addr;
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logic [1:0] buf_size;
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logic buf_write;
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logic [7:0] buf_byteen;
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logic buf_aligned;
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logic [63:0] buf_data;
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logic [TAG-1:0] buf_tag;
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//Miscellaneous signals
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logic buf_rst;
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logic [TAG-1:0] buf_tag_in;
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logic [31:0] buf_addr_in;
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logic [7:0] buf_byteen_in;
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logic [63:0] buf_data_in;
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logic buf_write_in;
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logic buf_aligned_in;
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logic [2:0] buf_size_in;
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logic buf_state_en;
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logic buf_wr_en;
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logic buf_data_wr_en;
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logic slvbuf_error_en;
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logic wr_cmd_vld;
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logic cmd_done_rst, cmd_done, cmd_doneQ;
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logic trxn_done;
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logic [2:0] buf_cmd_byte_ptr, buf_cmd_byte_ptrQ, buf_cmd_nxtbyte_ptr;
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logic buf_cmd_byte_ptr_en;
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logic found;
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logic slave_valid_pre;
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logic ahb_hready_q;
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logic ahb_hresp_q;
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logic [1:0] ahb_htrans_q;
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logic ahb_hwrite_q;
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logic [63:0] ahb_hrdata_q;
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logic slvbuf_write;
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logic slvbuf_error;
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logic [TAG-1:0] slvbuf_tag;
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logic slvbuf_error_in;
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logic slvbuf_wr_en;
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logic bypass_en;
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logic rd_bypass_idle;
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logic last_addr_en;
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logic [31:0] last_bus_addr;
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// Clocks
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logic buf_clken;
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logic ahbm_data_clken;
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logic buf_clk;
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logic bus_clk;
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logic ahbm_data_clk;
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logic dec_tlu_force_halt_bus, dec_tlu_force_halt_bus_ns, dec_tlu_force_halt_bus_q;
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// Function to get the length from byte enable
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function automatic logic [1:0] get_write_size;
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input logic [7:0] byteen;
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logic [1:0] size;
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size[1:0] = (2'b11 & {2{(byteen[7:0] == 8'hff)}}) |
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(2'b10 & {2{((byteen[7:0] == 8'hf0) | (byteen[7:0] == 8'h0f))}}) |
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(2'b01 & {2{((byteen[7:0] == 8'hc0) | (byteen[7:0] == 8'h30) | (byteen[7:0] == 8'h0c) | (byteen[7:0] == 8'h03))}});
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return size[1:0];
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endfunction // get_write_size
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// Function to get the length from byte enable
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function automatic logic [2:0] get_write_addr;
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input logic [7:0] byteen;
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logic [2:0] addr;
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addr[2:0] = (3'h0 & {3{((byteen[7:0] == 8'hff) | (byteen[7:0] == 8'h0f) | (byteen[7:0] == 8'h03))}}) |
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(3'h2 & {3{(byteen[7:0] == 8'h0c)}}) |
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(3'h4 & {3{((byteen[7:0] == 8'hf0) | (byteen[7:0] == 8'h03))}}) |
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(3'h6 & {3{(byteen[7:0] == 8'hc0)}});
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return addr[2:0];
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endfunction // get_write_addr
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// Function to get the next byte pointer
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function automatic logic [2:0] get_nxtbyte_ptr (logic [2:0] current_byte_ptr, logic [7:0] byteen, logic get_next);
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logic [2:0] start_ptr;
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logic found;
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found = '0;
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//get_nxtbyte_ptr[2:0] = current_byte_ptr[2:0];
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start_ptr[2:0] = get_next ? (current_byte_ptr[2:0] + 3'b1) : current_byte_ptr[2:0];
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for (int j=0; j<8; j++) begin
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if (~found) begin
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get_nxtbyte_ptr[2:0] = 3'(j);
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found |= (byteen[j] & (3'(j) >= start_ptr[2:0])) ;
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end
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end
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endfunction // get_nextbyte_ptr
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// Create bus synchronized version of force halt
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assign dec_tlu_force_halt_bus = dec_tlu_force_halt | dec_tlu_force_halt_bus_q;
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assign dec_tlu_force_halt_bus_ns = ~bus_clk_en & dec_tlu_force_halt_bus;
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rvdff #(.WIDTH(1)) force_halt_busff(.din(dec_tlu_force_halt_bus_ns), .dout(dec_tlu_force_halt_bus_q), .clk(free_clk), .*);
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// Write buffer
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assign wrbuf_en = axi_awvalid & axi_awready & master_ready;
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assign wrbuf_data_en = axi_wvalid & axi_wready & master_ready;
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assign wrbuf_cmd_sent = master_valid & master_ready & (master_opc[2:1] == 2'b01);
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assign wrbuf_rst = (wrbuf_cmd_sent & ~wrbuf_en) | dec_tlu_force_halt_bus;
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assign axi_awready = ~(wrbuf_vld & ~wrbuf_cmd_sent) & master_ready;
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assign axi_wready = ~(wrbuf_data_vld & ~wrbuf_cmd_sent) & master_ready;
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assign axi_arready = ~(wrbuf_vld & wrbuf_data_vld) & master_ready;
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assign axi_rlast = 1'b1;
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assign wr_cmd_vld = (wrbuf_vld & wrbuf_data_vld);
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assign master_valid = wr_cmd_vld | axi_arvalid;
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assign master_tag[TAG-1:0] = wr_cmd_vld ? wrbuf_tag[TAG-1:0] : axi_arid[TAG-1:0];
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assign master_opc[2:0] = wr_cmd_vld ? 3'b011 : 3'b0;
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assign master_addr[31:0] = wr_cmd_vld ? wrbuf_addr[31:0] : axi_araddr[31:0];
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assign master_size[2:0] = wr_cmd_vld ? wrbuf_size[2:0] : axi_arsize[2:0];
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assign master_byteen[7:0] = wrbuf_byteen[7:0];
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assign master_wdata[63:0] = wrbuf_data[63:0];
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// AXI response channel signals
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assign axi_bvalid = slave_valid & slave_ready & slave_opc[3];
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assign axi_bresp[1:0] = slave_opc[0] ? 2'b10 : (slave_opc[1] ? 2'b11 : 2'b0);
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assign axi_bid[TAG-1:0] = slave_tag[TAG-1:0];
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assign axi_rvalid = slave_valid & slave_ready & (slave_opc[3:2] == 2'b0);
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assign axi_rresp[1:0] = slave_opc[0] ? 2'b10 : (slave_opc[1] ? 2'b11 : 2'b0);
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assign axi_rid[TAG-1:0] = slave_tag[TAG-1:0];
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assign axi_rdata[63:0] = slave_rdata[63:0];
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assign slave_ready = axi_bready & axi_rready;
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// FIFO state machine
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always_comb begin
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buf_nxtstate = IDLE;
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buf_state_en = 1'b0;
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buf_wr_en = 1'b0;
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buf_data_wr_en = 1'b0;
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slvbuf_error_in = 1'b0;
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slvbuf_error_en = 1'b0;
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buf_write_in = 1'b0;
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cmd_done = 1'b0;
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trxn_done = 1'b0;
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buf_cmd_byte_ptr_en = 1'b0;
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buf_cmd_byte_ptr[2:0] = '0;
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slave_valid_pre = 1'b0;
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master_ready = 1'b0;
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ahb_htrans[1:0] = 2'b0;
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slvbuf_wr_en = 1'b0;
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bypass_en = 1'b0;
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rd_bypass_idle = 1'b0;
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case (buf_state)
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IDLE: begin
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master_ready = 1'b1;
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buf_write_in = (master_opc[2:1] == 2'b01);
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buf_nxtstate = buf_write_in ? CMD_WR : CMD_RD;
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buf_state_en = master_valid & master_ready;
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buf_wr_en = buf_state_en;
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buf_data_wr_en = buf_state_en & (buf_nxtstate == CMD_WR);
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buf_cmd_byte_ptr_en = buf_state_en;
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buf_cmd_byte_ptr[2:0] = buf_write_in ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) : master_addr[2:0];
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bypass_en = buf_state_en;
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rd_bypass_idle = bypass_en & (buf_nxtstate == CMD_RD);
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ahb_htrans[1:0] = {2{bypass_en}} & 2'b10;
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end
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CMD_RD: begin
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buf_nxtstate = (master_valid & (master_opc[2:0] == 3'b000))? STREAM_RD : DATA_RD;
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buf_state_en = ahb_hready_q & (ahb_htrans_q[1:0] != 2'b0) & ~ahb_hwrite_q;
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cmd_done = buf_state_en & ~master_valid;
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slvbuf_wr_en = buf_state_en;
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master_ready = buf_state_en & (buf_nxtstate == STREAM_RD);
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buf_wr_en = master_ready;
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bypass_en = master_ready & master_valid;
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buf_cmd_byte_ptr[2:0] = bypass_en ? master_addr[2:0] : buf_addr[2:0];
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ahb_htrans[1:0] = 2'b10 & {2{~buf_state_en | bypass_en}};
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end
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STREAM_RD: begin
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master_ready = (ahb_hready_q & ~ahb_hresp_q) & ~(master_valid & master_opc[2:1] == 2'b01);
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buf_wr_en = (master_valid & master_ready & (master_opc[2:0] == 3'b000)); // update the fifo if we are streaming the read commands
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buf_nxtstate = ahb_hresp_q ? STREAM_ERR_RD : (buf_wr_en ? STREAM_RD : DATA_RD); // assuming that the master accpets the slave response right away.
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buf_state_en = (ahb_hready_q | ahb_hresp_q);
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buf_data_wr_en = buf_state_en;
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slvbuf_error_in = ahb_hresp_q;
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slvbuf_error_en = buf_state_en;
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slave_valid_pre = buf_state_en & ~ahb_hresp_q; // send a response right away if we are not going through an error response.
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cmd_done = buf_state_en & ~master_valid; // last one of the stream should not send a htrans
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bypass_en = master_ready & master_valid & (buf_nxtstate == STREAM_RD) & buf_state_en;
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buf_cmd_byte_ptr[2:0] = bypass_en ? master_addr[2:0] : buf_addr[2:0];
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ahb_htrans[1:0] = 2'b10 & {2{~((buf_nxtstate != STREAM_RD) & buf_state_en)}};
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slvbuf_wr_en = buf_wr_en; // shifting the contents from the buf to slv_buf for streaming cases
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end // case: STREAM_RD
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STREAM_ERR_RD: begin
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buf_nxtstate = DATA_RD;
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buf_state_en = ahb_hready_q & (ahb_htrans_q[1:0] != 2'b0) & ~ahb_hwrite_q;
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slave_valid_pre = buf_state_en;
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slvbuf_wr_en = buf_state_en; // Overwrite slvbuf with buffer
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buf_cmd_byte_ptr[2:0] = buf_addr[2:0];
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ahb_htrans[1:0] = 2'b10 & {2{~buf_state_en}};
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end
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DATA_RD: begin
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buf_nxtstate = DONE;
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buf_state_en = (ahb_hready_q | ahb_hresp_q);
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buf_data_wr_en = buf_state_en;
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slvbuf_error_in= ahb_hresp_q;
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slvbuf_error_en= buf_state_en;
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slvbuf_wr_en = buf_state_en;
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end
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CMD_WR: begin
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buf_nxtstate = DATA_WR;
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trxn_done = ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q[1:0] != 2'b0);
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buf_state_en = trxn_done;
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buf_cmd_byte_ptr_en = buf_state_en;
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slvbuf_wr_en = buf_state_en;
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buf_cmd_byte_ptr = trxn_done ? get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1) : buf_cmd_byte_ptrQ;
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cmd_done = trxn_done & (buf_aligned | (buf_cmd_byte_ptrQ == 3'b111) |
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(buf_byteen[get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1)] == 1'b0));
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ahb_htrans[1:0] = {2{~(cmd_done | cmd_doneQ)}} & 2'b10;
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end
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DATA_WR: begin
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buf_state_en = (cmd_doneQ & ahb_hready_q) | ahb_hresp_q;
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master_ready = buf_state_en & ~ahb_hresp_q & slave_ready; // Ready to accept new command if current command done and no error
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buf_nxtstate = (ahb_hresp_q | ~slave_ready) ? DONE :
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((master_valid & master_ready) ? ((master_opc[2:1] == 2'b01) ? CMD_WR : CMD_RD) : IDLE);
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slvbuf_error_in = ahb_hresp_q;
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slvbuf_error_en = buf_state_en;
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buf_write_in = (master_opc[2:1] == 2'b01);
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buf_wr_en = buf_state_en & ((buf_nxtstate == CMD_WR) | (buf_nxtstate == CMD_RD));
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buf_data_wr_en = buf_wr_en;
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cmd_done = (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q[1:0] != 2'b0) &
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((buf_cmd_byte_ptrQ == 3'b111) | (buf_byteen[get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1)] == 1'b0))));
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bypass_en = buf_state_en & buf_write_in & (buf_nxtstate == CMD_WR); // Only bypass for writes for the time being
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ahb_htrans[1:0] = {2{(~(cmd_done | cmd_doneQ) | bypass_en)}} & 2'b10;
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slave_valid_pre = buf_state_en & (buf_nxtstate != DONE);
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trxn_done = ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q[1:0] != 2'b0);
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buf_cmd_byte_ptr_en = trxn_done | bypass_en;
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buf_cmd_byte_ptr = bypass_en ? get_nxtbyte_ptr(3'b0,buf_byteen_in[7:0],1'b0) :
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trxn_done ? get_nxtbyte_ptr(buf_cmd_byte_ptrQ[2:0],buf_byteen[7:0],1'b1) : buf_cmd_byte_ptrQ;
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end
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DONE: begin
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buf_nxtstate = IDLE;
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buf_state_en = slave_ready;
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slvbuf_error_en = 1'b1;
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slave_valid_pre = 1'b1;
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end
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endcase
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end
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assign buf_rst = dec_tlu_force_halt_bus;
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assign cmd_done_rst = slave_valid_pre;
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assign buf_addr_in[31:3] = master_addr[31:3];
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assign buf_addr_in[2:0] = (buf_aligned_in & (master_opc[2:1] == 2'b01)) ? get_write_addr(master_byteen[7:0]) : master_addr[2:0];
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assign buf_tag_in[TAG-1:0] = master_tag[TAG-1:0];
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assign buf_byteen_in[7:0] = wrbuf_byteen[7:0];
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assign buf_data_in[63:0] = (buf_state == DATA_RD) ? ahb_hrdata_q[63:0] : master_wdata[63:0];
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assign buf_size_in[1:0] = (buf_aligned_in & (master_size[1:0] == 2'b11) & (master_opc[2:1] == 2'b01)) ? get_write_size(master_byteen[7:0]) : master_size[1:0];
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assign buf_aligned_in = (master_opc[2:0] == 3'b0) | // reads are always aligned since they are either DW or sideeffects
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(master_size[1:0] == 2'b0) | (master_size[1:0] == 2'b01) | (master_size[1:0] == 2'b10) | // Always aligned for Byte/HW/Word since they can be only for non-idempotent. IFU/SB are always aligned
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((master_size[1:0] == 2'b11) &
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((master_byteen[7:0] == 8'h3) | (master_byteen[7:0] == 8'hc) | (master_byteen[7:0] == 8'h30) | (master_byteen[7:0] == 8'hc0) |
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(master_byteen[7:0] == 8'hf) | (master_byteen[7:0] == 8'hf0) | (master_byteen[7:0] == 8'hff)));
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// Generate the ahb signals
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assign ahb_haddr[31:3] = bypass_en ? master_addr[31:3] : buf_addr[31:3];
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assign ahb_haddr[2:0] = {3{(ahb_htrans == 2'b10)}} & buf_cmd_byte_ptr[2:0]; // Trxn should be aligned during IDLE
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assign ahb_hsize[2:0] = bypass_en ? {1'b0, ({2{buf_aligned_in}} & buf_size_in[1:0])} :
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{1'b0, ({2{buf_aligned}} & buf_size[1:0])}; // Send the full size for aligned trxn
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assign ahb_hburst[2:0] = 3'b0;
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assign ahb_hmastlock = 1'b0;
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assign ahb_hprot[3:0] = {3'b001,~axi_arprot[2]};
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assign ahb_hwrite = bypass_en ? (master_opc[2:1] == 2'b01) : buf_write;
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assign ahb_hwdata[63:0] = buf_data[63:0];
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assign slave_valid = slave_valid_pre;// & (~slvbuf_posted_write | slvbuf_error);
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assign slave_opc[3:2] = slvbuf_write ? 2'b11 : 2'b00;
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assign slave_opc[1:0] = {2{slvbuf_error}} & 2'b10;
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assign slave_rdata[63:0] = slvbuf_error ? {2{last_bus_addr[31:0]}} : ((buf_state == DONE) ? buf_data[63:0] : ahb_hrdata_q[63:0]);
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assign slave_tag[TAG-1:0] = slvbuf_tag[TAG-1:0];
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assign last_addr_en = (ahb_htrans[1:0] != 2'b0) & ahb_hready & ahb_hwrite ;
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rvdffsc_fpga #(.WIDTH(1)) wrbuf_vldff (.din(1'b1), .dout(wrbuf_vld), .en(wrbuf_en), .clear(wrbuf_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdffsc_fpga #(.WIDTH(1)) wrbuf_data_vldff(.din(1'b1), .dout(wrbuf_data_vld), .en(wrbuf_data_en), .clear(wrbuf_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdffs_fpga #(.WIDTH(TAG)) wrbuf_tagff (.din(axi_awid[TAG-1:0]), .dout(wrbuf_tag[TAG-1:0]), .en(wrbuf_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdffs_fpga #(.WIDTH(3)) wrbuf_sizeff (.din(axi_awsize[2:0]), .dout(wrbuf_size[2:0]), .en(wrbuf_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdffe #(.WIDTH(32)) wrbuf_addrff (.din(axi_awaddr[31:0]), .dout(wrbuf_addr[31:0]), .en(wrbuf_en & bus_clk_en), .clk(clk), .*);
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rvdffe #(.WIDTH(64)) wrbuf_dataff (.din(axi_wdata[63:0]), .dout(wrbuf_data[63:0]), .en(wrbuf_data_en & bus_clk_en), .clk(clk), .*);
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rvdffs_fpga #(.WIDTH(8)) wrbuf_byteenff (.din(axi_wstrb[7:0]), .dout(wrbuf_byteen[7:0]), .en(wrbuf_data_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdffs_fpga #(.WIDTH(32)) last_bus_addrff (.din(ahb_haddr[31:0]), .dout(last_bus_addr[31:0]), .en(last_addr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdffsc_fpga #(.WIDTH($bits(state_t))) buf_state_ff (.din(buf_nxtstate), .dout({buf_state}), .en(buf_state_en), .clear(buf_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdffs_fpga #(.WIDTH(1)) buf_writeff (.din(buf_write_in), .dout(buf_write), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
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rvdffs_fpga #(.WIDTH(TAG)) buf_tagff (.din(buf_tag_in[TAG-1:0]), .dout(buf_tag[TAG-1:0]), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
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rvdffe #(.WIDTH(32)) buf_addrff (.din(buf_addr_in[31:0]), .dout(buf_addr[31:0]), .en(buf_wr_en & bus_clk_en), .clk(clk), .*);
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rvdffs_fpga #(.WIDTH(2)) buf_sizeff (.din(buf_size_in[1:0]), .dout(buf_size[1:0]), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
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rvdffs_fpga #(.WIDTH(1)) buf_alignedff (.din(buf_aligned_in), .dout(buf_aligned), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
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rvdffs_fpga #(.WIDTH(8)) buf_byteenff (.din(buf_byteen_in[7:0]), .dout(buf_byteen[7:0]), .en(buf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
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rvdffe #(.WIDTH(64)) buf_dataff (.din(buf_data_in[63:0]), .dout(buf_data[63:0]), .en(buf_data_wr_en & bus_clk_en), .clk(clk), .*);
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rvdffs_fpga #(.WIDTH(1)) slvbuf_writeff (.din(buf_write), .dout(slvbuf_write), .en(slvbuf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
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rvdffs_fpga #(.WIDTH(TAG)) slvbuf_tagff (.din(buf_tag[TAG-1:0]), .dout(slvbuf_tag[TAG-1:0]), .en(slvbuf_wr_en), .clk(buf_clk), .clken(buf_clken), .rawclk(clk), .*);
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rvdffs_fpga #(.WIDTH(1)) slvbuf_errorff (.din(slvbuf_error_in), .dout(slvbuf_error), .en(slvbuf_error_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdffsc_fpga #(.WIDTH(1)) buf_cmd_doneff (.din(1'b1), .dout(cmd_doneQ), .en(cmd_done), .clear(cmd_done_rst), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdffs_fpga #(.WIDTH(3)) buf_cmd_byte_ptrff (.din(buf_cmd_byte_ptr[2:0]), .dout(buf_cmd_byte_ptrQ[2:0]), .en(buf_cmd_byte_ptr_en), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdff_fpga #(.WIDTH(1)) hready_ff (.din(ahb_hready), .dout(ahb_hready_q), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdff_fpga #(.WIDTH(2)) htrans_ff (.din(ahb_htrans[1:0]), .dout(ahb_htrans_q[1:0]), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdff_fpga #(.WIDTH(1)) hwrite_ff (.din(ahb_hwrite), .dout(ahb_hwrite_q), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdff_fpga #(.WIDTH(1)) hresp_ff (.din(ahb_hresp), .dout(ahb_hresp_q), .clk(bus_clk), .clken(bus_clk_en), .rawclk(clk), .*);
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rvdff_fpga #(.WIDTH(64)) hrdata_ff (.din(ahb_hrdata[63:0]), .dout(ahb_hrdata_q[63:0]), .clk(ahbm_data_clk), .clken(ahbm_data_clken), .rawclk(clk), .*);
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// Clock headers
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// clock enables for ahbm addr/data
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assign buf_clken = bus_clk_en & (buf_wr_en | slvbuf_wr_en | clk_override);
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assign ahbm_data_clken = bus_clk_en & ((buf_state != IDLE) | clk_override);
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`ifdef RV_FPGA_OPTIMIZE
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assign bus_clk = 1'b0;
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assign buf_clk = 1'b0;
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assign ahbm_data_clk = 1'b0;
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`else
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rvclkhdr bus_cgc (.en(bus_clk_en), .l1clk(bus_clk), .*);
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rvclkhdr buf_cgc (.en(buf_clken), .l1clk(buf_clk), .*);
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rvclkhdr ahbm_data_cgc (.en(ahbm_data_clken), .l1clk(ahbm_data_clk), .*);
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`endif
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`ifdef RV_ASSERT_ON
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property ahb_trxn_aligned;
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@(posedge bus_clk) ahb_htrans[1] |-> ((ahb_hsize[2:0] == 3'h0) |
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((ahb_hsize[2:0] == 3'h1) & (ahb_haddr[0] == 1'b0)) |
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((ahb_hsize[2:0] == 3'h2) & (ahb_haddr[1:0] == 2'b0)) |
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((ahb_hsize[2:0] == 3'h3) & (ahb_haddr[2:0] == 3'b0)));
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endproperty
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assert_ahb_trxn_aligned: assert property (ahb_trxn_aligned) else
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$display("Assertion ahb_trxn_aligned failed: ahb_htrans=2'h%h, ahb_hsize=3'h%h, ahb_haddr=32'h%h",ahb_htrans[1:0], ahb_hsize[2:0], ahb_haddr[31:0]);
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property ahb_error_protocol;
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@(posedge bus_clk) (ahb_hready & ahb_hresp) |-> (~$past(ahb_hready) & $past(ahb_hresp));
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endproperty
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assert_ahb_error_protocol: assert property (ahb_error_protocol) else
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$display("Bus Error with hReady isn't preceded with Bus Error without hready");
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`endif
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endmodule // axi4_to_ahb
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