342 lines
19 KiB
Systemverilog
342 lines
19 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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//
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// Owner:
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// Function: LSU control
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// Comments:
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//
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//
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// DC1 -> DC2 -> DC3 -> DC4 (Commit)
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//
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//********************************************************************************
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module el2_lsu_lsc_ctl
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import el2_pkg::*;
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#(
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`include "el2_param.vh"
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)(
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input logic rst_l, // reset, active low
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input logic clk_override, // Override non-functional clock gating
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input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
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// clocks per pipe
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input logic lsu_c1_m_clk,
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input logic lsu_c1_r_clk,
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input logic lsu_c2_m_clk,
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input logic lsu_c2_r_clk,
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input logic lsu_store_c1_m_clk,
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input logic [31:0] lsu_ld_data_r, // Load data R-stage
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input logic [31:0] lsu_ld_data_corr_r, // ECC corrected data R-stage
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input logic lsu_single_ecc_error_r, // ECC single bit error R-stage
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input logic lsu_double_ecc_error_r, // ECC double bit error R-stage
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input logic [31:0] lsu_ld_data_m, // Load data M-stage
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input logic lsu_single_ecc_error_m, // ECC single bit error M-stage
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input logic lsu_double_ecc_error_m, // ECC double bit error M-stage
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input logic flush_m_up, // Flush M and D stage
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input logic flush_r, // Flush R-stage
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input logic ldst_dual_d, // load/store is unaligned at 32 bit boundary D-stage
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input logic ldst_dual_m, // load/store is unaligned at 32 bit boundary M-stage
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input logic ldst_dual_r, // load/store is unaligned at 32 bit boundary R-stage
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input logic [31:0] exu_lsu_rs1_d, // address
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input logic [31:0] exu_lsu_rs2_d, // store data
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input el2_lsu_pkt_t lsu_p, // lsu control packet
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input logic dec_lsu_valid_raw_d, // Raw valid for address computation
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input logic [11:0] dec_lsu_offset_d, // 12b offset for load/store addresses
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input logic [31:0] picm_mask_data_m, // PIC data M-stage
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input logic [31:0] bus_read_data_m, // the bus return data
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output logic [31:0] lsu_result_m, // lsu load data
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output logic [31:0] lsu_result_corr_r, // This is the ECC corrected data going to RF
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// lsu address down the pipe
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output logic [31:0] lsu_addr_d,
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output logic [31:0] lsu_addr_m,
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output logic [31:0] lsu_addr_r,
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// lsu address down the pipe - needed to check unaligned
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output logic [31:0] end_addr_d,
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output logic [31:0] end_addr_m,
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output logic [31:0] end_addr_r,
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// store data down the pipe
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output logic [31:0] store_data_m,
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input logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control
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output logic lsu_exc_m, // Access or misaligned fault
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output logic is_sideeffects_m, // is sideffects space
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output logic lsu_commit_r, // lsu instruction in r commits
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output logic lsu_single_ecc_error_incr,// LSU inc SB error counter
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output el2_lsu_error_pkt_t lsu_error_pkt_r, // lsu exception packet
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output logic [31:1] lsu_fir_addr, // fast interrupt address
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output logic [1:0] lsu_fir_error, // Error during fast interrupt lookup
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// address in dccm/pic/external per pipe stage
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output logic addr_in_dccm_d,
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output logic addr_in_dccm_m,
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output logic addr_in_dccm_r,
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output logic addr_in_pic_d,
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output logic addr_in_pic_m,
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output logic addr_in_pic_r,
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output logic addr_external_m,
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// DMA slave
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input logic dma_dccm_req,
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input logic [31:0] dma_mem_addr,
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input logic [2:0] dma_mem_sz,
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input logic dma_mem_write,
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input logic [63:0] dma_mem_wdata,
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// Store buffer related signals
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output el2_lsu_pkt_t lsu_pkt_d,
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output el2_lsu_pkt_t lsu_pkt_m,
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output el2_lsu_pkt_t lsu_pkt_r,
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input logic scan_mode // Scan mode
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);
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logic [31:3] end_addr_pre_m, end_addr_pre_r;
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logic [31:0] full_addr_d;
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logic [31:0] full_end_addr_d;
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logic [31:0] lsu_rs1_d;
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logic [11:0] lsu_offset_d;
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logic [31:0] rs1_d;
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logic [11:0] offset_d;
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logic [12:0] end_addr_offset_d;
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logic [2:0] addr_offset_d;
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logic [63:0] dma_mem_wdata_shifted;
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logic addr_external_d;
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logic addr_external_r;
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logic access_fault_d, misaligned_fault_d;
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logic access_fault_m, misaligned_fault_m;
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logic fir_dccm_access_error_d, fir_nondccm_access_error_d;
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logic fir_dccm_access_error_m, fir_nondccm_access_error_m;
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logic [3:0] exc_mscause_d, exc_mscause_m;
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logic [31:0] rs1_d_raw;
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logic [31:0] store_data_d, store_data_pre_m, store_data_m_in;
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logic [31:0] bus_read_data_r;
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el2_lsu_pkt_t dma_pkt_d;
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el2_lsu_pkt_t lsu_pkt_m_in, lsu_pkt_r_in;
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el2_lsu_error_pkt_t lsu_error_pkt_m;
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// Premux the rs1/offset for dma
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assign lsu_rs1_d[31:0] = dec_lsu_valid_raw_d ? exu_lsu_rs1_d[31:0] : dma_mem_addr[31:0];
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assign lsu_offset_d[11:0] = dec_lsu_offset_d[11:0] & {12{dec_lsu_valid_raw_d}};
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assign rs1_d_raw[31:0] = lsu_rs1_d[31:0];
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assign offset_d[11:0] = lsu_offset_d[11:0];
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assign rs1_d[31:0] = (lsu_pkt_d.load_ldst_bypass_d) ? lsu_result_m[31:0] : rs1_d_raw[31:0];
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// generate the ls address
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rvlsadder lsadder (.rs1(rs1_d[31:0]),
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.offset(offset_d[11:0]),
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.dout(full_addr_d[31:0])
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);
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// Module to generate the memory map of the address
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el2_lsu_addrcheck addrcheck (
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.start_addr_d(full_addr_d[31:0]),
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.end_addr_d(full_end_addr_d[31:0]),
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.rs1_region_d(rs1_d[31:28]),
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.*
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);
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// Calculate start/end address for load/store
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assign addr_offset_d[2:0] = ({3{lsu_pkt_d.half}} & 3'b01) | ({3{lsu_pkt_d.word}} & 3'b11) | ({3{lsu_pkt_d.dword}} & 3'b111);
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assign end_addr_offset_d[12:0] = {offset_d[11],offset_d[11:0]} + {9'b0,addr_offset_d[2:0]};
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assign full_end_addr_d[31:0] = rs1_d[31:0] + {{19{end_addr_offset_d[12]}},end_addr_offset_d[12:0]};
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assign end_addr_d[31:0] = full_end_addr_d[31:0];
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assign lsu_exc_m = access_fault_m | misaligned_fault_m;
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// Goes to TLU to increment the ECC error counter
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assign lsu_single_ecc_error_incr = (lsu_single_ecc_error_r & ~lsu_double_ecc_error_r) & (lsu_commit_r | lsu_pkt_r.dma) & lsu_pkt_r.valid;
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if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U_Plus1_1
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logic access_fault_r, misaligned_fault_r;
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logic [3:0] exc_mscause_r;
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logic fir_dccm_access_error_r, fir_nondccm_access_error_r;
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// Generate exception packet
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assign lsu_error_pkt_r.exc_valid = (access_fault_r | misaligned_fault_r | lsu_double_ecc_error_r) & lsu_pkt_r.valid & ~lsu_pkt_r.dma & ~lsu_pkt_r.fast_int;
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assign lsu_error_pkt_r.single_ecc_error = lsu_single_ecc_error_r & ~lsu_error_pkt_r.exc_valid & ~lsu_pkt_r.dma;
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assign lsu_error_pkt_r.inst_type = lsu_pkt_r.store;
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assign lsu_error_pkt_r.exc_type = ~misaligned_fault_r;
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assign lsu_error_pkt_r.mscause[3:0] = (lsu_double_ecc_error_r & ~misaligned_fault_r & ~access_fault_r) ? 4'h1 : exc_mscause_r[3:0];
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assign lsu_error_pkt_r.addr[31:0] = lsu_addr_r[31:0];
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assign lsu_fir_error[1:0] = fir_nondccm_access_error_r ? 2'b11 : (fir_dccm_access_error_r ? 2'b10 : ((lsu_pkt_r.fast_int & lsu_double_ecc_error_r) ? 2'b01 : 2'b00));
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rvdff #(1) access_fault_rff (.din(access_fault_m), .dout(access_fault_r), .clk(lsu_c1_r_clk), .*);
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rvdff #(1) misaligned_fault_rff (.din(misaligned_fault_m), .dout(misaligned_fault_r), .clk(lsu_c1_r_clk), .*);
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rvdff #(4) exc_mscause_rff (.din(exc_mscause_m[3:0]), .dout(exc_mscause_r[3:0]), .clk(lsu_c1_r_clk), .*);
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rvdff #(1) fir_dccm_access_error_mff (.din(fir_dccm_access_error_m), .dout(fir_dccm_access_error_r), .clk(lsu_c1_r_clk), .*);
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rvdff #(1) fir_nondccm_access_error_mff (.din(fir_nondccm_access_error_m), .dout(fir_nondccm_access_error_r), .clk(lsu_c1_r_clk), .*);
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end else begin: L2U_Plus1_0
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logic [1:0] lsu_fir_error_m;
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// Generate exception packet
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assign lsu_error_pkt_m.exc_valid = (access_fault_m | misaligned_fault_m | lsu_double_ecc_error_m) & lsu_pkt_m.valid & ~lsu_pkt_m.dma & ~lsu_pkt_m.fast_int & ~flush_m_up;
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assign lsu_error_pkt_m.single_ecc_error = lsu_single_ecc_error_m & ~lsu_error_pkt_m.exc_valid & ~lsu_pkt_m.dma;
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assign lsu_error_pkt_m.inst_type = lsu_pkt_m.store;
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assign lsu_error_pkt_m.exc_type = ~misaligned_fault_m;
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assign lsu_error_pkt_m.mscause[3:0] = (lsu_double_ecc_error_m & ~misaligned_fault_m & ~access_fault_m) ? 4'h1 : exc_mscause_m[3:0];
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assign lsu_error_pkt_m.addr[31:0] = lsu_addr_m[31:0];
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assign lsu_fir_error_m[1:0] = fir_nondccm_access_error_m ? 2'b11 : (fir_dccm_access_error_m ? 2'b10 : ((lsu_pkt_m.fast_int & lsu_double_ecc_error_m) ? 2'b01 : 2'b00));
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rvdff #(1) lsu_exc_valid_rff (.*, .din(lsu_error_pkt_m.exc_valid), .dout(lsu_error_pkt_r.exc_valid), .clk(lsu_c2_r_clk));
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rvdff #(1) lsu_single_ecc_error_rff(.*, .din(lsu_error_pkt_m.single_ecc_error), .dout(lsu_error_pkt_r.single_ecc_error), .clk(lsu_c2_r_clk));
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rvdffe #($bits(el2_lsu_error_pkt_t)-2) lsu_error_pkt_rff (.*, .din(lsu_error_pkt_m[$bits(el2_lsu_error_pkt_t)-1:2]), .dout(lsu_error_pkt_r[$bits(el2_lsu_error_pkt_t)-1:2]), .en(lsu_error_pkt_m.exc_valid | lsu_error_pkt_m.single_ecc_error | clk_override));
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rvdff #(2) lsu_fir_error_rff (.*, .din(lsu_fir_error_m[1:0]), .dout(lsu_fir_error[1:0]), .clk(lsu_c2_r_clk));
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end
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//Create DMA packet
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always_comb begin
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dma_pkt_d = '0;
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dma_pkt_d.valid = dma_dccm_req;
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dma_pkt_d.dma = 1'b1;
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dma_pkt_d.store = dma_mem_write;
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dma_pkt_d.load = ~dma_mem_write;
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dma_pkt_d.by = (dma_mem_sz[2:0] == 3'b0);
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dma_pkt_d.half = (dma_mem_sz[2:0] == 3'b1);
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dma_pkt_d.word = (dma_mem_sz[2:0] == 3'b10);
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dma_pkt_d.dword = (dma_mem_sz[2:0] == 3'b11);
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end
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always_comb begin
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lsu_pkt_d = dec_lsu_valid_raw_d ? lsu_p : dma_pkt_d;
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lsu_pkt_m_in = lsu_pkt_d;
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lsu_pkt_r_in = lsu_pkt_m;
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lsu_pkt_d.valid = (lsu_p.valid & ~(flush_m_up & ~lsu_p.fast_int)) | dma_dccm_req;
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lsu_pkt_m_in.valid = lsu_pkt_d.valid & ~(flush_m_up & ~lsu_pkt_d.dma);
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lsu_pkt_r_in.valid = lsu_pkt_m.valid & ~(flush_m_up & ~lsu_pkt_m.dma) ;
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end
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// C2 clock for valid and C1 for other bits of packet
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rvdff #(1) lsu_pkt_vldmff (.*, .din(lsu_pkt_m_in.valid), .dout(lsu_pkt_m.valid), .clk(lsu_c2_m_clk));
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rvdff #(1) lsu_pkt_vldrff (.*, .din(lsu_pkt_r_in.valid), .dout(lsu_pkt_r.valid), .clk(lsu_c2_r_clk));
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rvdff #($bits(el2_lsu_pkt_t)-1) lsu_pkt_mff (.*, .din(lsu_pkt_m_in[$bits(el2_lsu_pkt_t)-1:1]), .dout(lsu_pkt_m[$bits(el2_lsu_pkt_t)-1:1]), .clk(lsu_c1_m_clk));
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rvdff #($bits(el2_lsu_pkt_t)-1) lsu_pkt_rff (.*, .din(lsu_pkt_r_in[$bits(el2_lsu_pkt_t)-1:1]), .dout(lsu_pkt_r[$bits(el2_lsu_pkt_t)-1:1]), .clk(lsu_c1_r_clk));
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if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U1_Plus1_1
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logic [31:0] lsu_ld_datafn_r, lsu_ld_datafn_corr_r;
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assign lsu_ld_datafn_r[31:0] = addr_external_r ? bus_read_data_r[31:0] : lsu_ld_data_r[31:0];
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assign lsu_ld_datafn_corr_r[31:0] = addr_external_r ? bus_read_data_r[31:0] : lsu_ld_data_corr_r[31:0];
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// this is really R stage signal
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assign lsu_result_m[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by }} & {24'b0,lsu_ld_datafn_r[7:0]}) |
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({32{ lsu_pkt_r.unsign & lsu_pkt_r.half}} & {16'b0,lsu_ld_datafn_r[15:0]}) |
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({32{~lsu_pkt_r.unsign & lsu_pkt_r.by }} & {{24{ lsu_ld_datafn_r[7]}}, lsu_ld_datafn_r[7:0]}) |
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({32{~lsu_pkt_r.unsign & lsu_pkt_r.half}} & {{16{ lsu_ld_datafn_r[15]}},lsu_ld_datafn_r[15:0]}) |
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({32{lsu_pkt_r.word}} & lsu_ld_datafn_r[31:0]);
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// this signal is used for gpr update
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assign lsu_result_corr_r[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by }} & {24'b0,lsu_ld_datafn_corr_r[7:0]}) |
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({32{ lsu_pkt_r.unsign & lsu_pkt_r.half}} & {16'b0,lsu_ld_datafn_corr_r[15:0]}) |
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({32{~lsu_pkt_r.unsign & lsu_pkt_r.by }} & {{24{ lsu_ld_datafn_corr_r[7]}}, lsu_ld_datafn_corr_r[7:0]}) |
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({32{~lsu_pkt_r.unsign & lsu_pkt_r.half}} & {{16{ lsu_ld_datafn_corr_r[15]}},lsu_ld_datafn_corr_r[15:0]}) |
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({32{lsu_pkt_r.word}} & lsu_ld_datafn_corr_r[31:0]);
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end else begin: L2U1_Plus1_0 // block: L2U1_Plus1_1
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logic [31:0] lsu_ld_datafn_m, lsu_ld_datafn_corr_r;
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assign lsu_ld_datafn_m[31:0] = addr_external_m ? bus_read_data_m[31:0] : lsu_ld_data_m[31:0];
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assign lsu_ld_datafn_corr_r[31:0] = addr_external_r ? bus_read_data_r[31:0] : lsu_ld_data_corr_r[31:0];
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// this result must look at prior stores and merge them in
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assign lsu_result_m[31:0] = ({32{ lsu_pkt_m.unsign & lsu_pkt_m.by }} & {24'b0,lsu_ld_datafn_m[7:0]}) |
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({32{ lsu_pkt_m.unsign & lsu_pkt_m.half}} & {16'b0,lsu_ld_datafn_m[15:0]}) |
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({32{~lsu_pkt_m.unsign & lsu_pkt_m.by }} & {{24{ lsu_ld_datafn_m[7]}}, lsu_ld_datafn_m[7:0]}) |
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({32{~lsu_pkt_m.unsign & lsu_pkt_m.half}} & {{16{ lsu_ld_datafn_m[15]}},lsu_ld_datafn_m[15:0]}) |
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({32{lsu_pkt_m.word}} & lsu_ld_datafn_m[31:0]);
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// this signal is used for gpr update
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assign lsu_result_corr_r[31:0] = ({32{ lsu_pkt_r.unsign & lsu_pkt_r.by }} & {24'b0,lsu_ld_datafn_corr_r[7:0]}) |
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({32{ lsu_pkt_r.unsign & lsu_pkt_r.half}} & {16'b0,lsu_ld_datafn_corr_r[15:0]}) |
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({32{~lsu_pkt_r.unsign & lsu_pkt_r.by }} & {{24{ lsu_ld_datafn_corr_r[7]}}, lsu_ld_datafn_corr_r[7:0]}) |
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({32{~lsu_pkt_r.unsign & lsu_pkt_r.half}} & {{16{ lsu_ld_datafn_corr_r[15]}},lsu_ld_datafn_corr_r[15:0]}) |
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({32{lsu_pkt_r.word}} & lsu_ld_datafn_corr_r[31:0]);
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end
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// Fast interrupt address
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assign lsu_fir_addr[31:1] = lsu_ld_data_corr_r[31:1];
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// absence load/store all 0's
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assign lsu_addr_d[31:0] = full_addr_d[31:0];
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// Interrupt as a flush source allows the WB to occur
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assign lsu_commit_r = lsu_pkt_r.valid & (lsu_pkt_r.store | lsu_pkt_r.load) & ~flush_r & ~lsu_pkt_r.dma;
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assign dma_mem_wdata_shifted[63:0] = dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}; // Shift the dma data to lower bits to make it consistent to lsu stores
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assign store_data_d[31:0] = dma_dccm_req ? dma_mem_wdata_shifted[31:0] : exu_lsu_rs2_d[31:0]; // Write to PIC still happens in r stage
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assign store_data_m_in[31:0] = (lsu_pkt_d.store_data_bypass_d) ? lsu_result_m[31:0] : store_data_d[31:0];
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assign store_data_m[31:0] = (picm_mask_data_m[31:0] | {32{~addr_in_pic_m}}) & ((lsu_pkt_m.store_data_bypass_m) ? lsu_result_m[31:0] : store_data_pre_m[31:0]);
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rvdff #(32) sdmff (.*, .din(store_data_m_in[31:0]), .dout(store_data_pre_m[31:0]), .clk(lsu_store_c1_m_clk));
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rvdff #(32) samff (.*, .din(lsu_addr_d[31:0]), .dout(lsu_addr_m[31:0]), .clk(lsu_c1_m_clk));
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rvdff #(32) sarff (.*, .din(lsu_addr_m[31:0]), .dout(lsu_addr_r[31:0]), .clk(lsu_c1_r_clk));
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assign end_addr_m[31:3] = ldst_dual_m ? end_addr_pre_m[31:3] : lsu_addr_m[31:3]; // This is for power saving
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assign end_addr_r[31:3] = ldst_dual_r ? end_addr_pre_r[31:3] : lsu_addr_r[31:3]; // This is for power saving
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rvdffe #(29) end_addr_hi_mff (.*, .din(end_addr_d[31:3]), .dout(end_addr_pre_m[31:3]), .en((lsu_pkt_d.valid & ldst_dual_d) | clk_override));
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rvdffe #(29) end_addr_hi_rff (.*, .din(end_addr_m[31:3]), .dout(end_addr_pre_r[31:3]), .en((lsu_pkt_m.valid & ldst_dual_m) | clk_override));
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rvdff #(3) end_addr_lo_mff (.*, .din(end_addr_d[2:0]), .dout(end_addr_m[2:0]), .clk(lsu_c1_m_clk));
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rvdff #(3) end_addr_lo_rff (.*, .din(end_addr_m[2:0]), .dout(end_addr_r[2:0]), .clk(lsu_c1_r_clk));
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rvdff #(1) addr_in_dccm_mff(.din(addr_in_dccm_d), .dout(addr_in_dccm_m), .clk(lsu_c1_m_clk), .*);
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rvdff #(1) addr_in_dccm_rff(.din(addr_in_dccm_m), .dout(addr_in_dccm_r), .clk(lsu_c1_r_clk), .*);
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rvdff #(1) addr_in_pic_mff(.din(addr_in_pic_d), .dout(addr_in_pic_m), .clk(lsu_c1_m_clk), .*);
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rvdff #(1) addr_in_pic_rff(.din(addr_in_pic_m), .dout(addr_in_pic_r), .clk(lsu_c1_r_clk), .*);
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rvdff #(1) addr_external_mff(.din(addr_external_d), .dout(addr_external_m), .clk(lsu_c1_m_clk), .*);
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rvdff #(1) addr_external_rff(.din(addr_external_m), .dout(addr_external_r), .clk(lsu_c1_r_clk), .*);
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rvdff #(1) access_fault_mff (.din(access_fault_d), .dout(access_fault_m), .clk(lsu_c1_m_clk), .*);
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rvdff #(1) misaligned_fault_mff (.din(misaligned_fault_d), .dout(misaligned_fault_m), .clk(lsu_c1_m_clk), .*);
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rvdff #(4) exc_mscause_mff (.din(exc_mscause_d[3:0]), .dout(exc_mscause_m[3:0]), .clk(lsu_c1_m_clk), .*);
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rvdff #(1) fir_dccm_access_error_mff (.din(fir_dccm_access_error_d), .dout(fir_dccm_access_error_m), .clk(lsu_c1_m_clk), .*);
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rvdff #(1) fir_nondccm_access_error_mff (.din(fir_nondccm_access_error_d), .dout(fir_nondccm_access_error_m), .clk(lsu_c1_m_clk), .*);
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rvdffe #(32) bus_read_data_r_ff (.*, .din(bus_read_data_m[31:0]), .dout(bus_read_data_r[31:0]), .en(addr_external_m | clk_override));
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endmodule
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