138 lines
6.5 KiB
Systemverilog
138 lines
6.5 KiB
Systemverilog
// Copyright 2020 Western Digital Corporation or it's affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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//
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// Owner:
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// Function: Clock Generation Block
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// Comments: All the clocks are generate here
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//
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// //********************************************************************************
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module el2_lsu_clkdomain
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import el2_pkg::*;
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#(
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`include "el2_param.vh"
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)(
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input logic clk, // clock
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input logic free_clk, // clock
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input logic rst_l, // reset
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// Inputs
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input logic clk_override, // chciken bit to turn off clock gating
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input logic addr_in_dccm_m, // address in dccm
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input logic dma_dccm_req, // dma is active
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input logic ldst_stbuf_reqvld_r, // allocating in to the store queue
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input logic stbuf_reqvld_any, // stbuf is draining
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input logic stbuf_reqvld_flushed_any, // instruction going to stbuf is flushed
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input logic lsu_busreq_r, // busreq in r
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input logic lsu_bus_buffer_pend_any, // bus buffer has a pending bus entry
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input logic lsu_bus_buffer_empty_any, // external bus buffer is empty
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input logic lsu_stbuf_empty_any, // stbuf is empty
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input logic lsu_bus_clk_en, // bus clock enable
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input el2_lsu_pkt_t lsu_p, // lsu packet in decode
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input el2_lsu_pkt_t lsu_pkt_d, // lsu packet in d
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input el2_lsu_pkt_t lsu_pkt_m, // lsu packet in m
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input el2_lsu_pkt_t lsu_pkt_r, // lsu packet in r
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// Outputs
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output logic lsu_c1_m_clk, // m pipe single pulse clock
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output logic lsu_c1_r_clk, // r pipe single pulse clock
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output logic lsu_c2_m_clk, // m pipe double pulse clock
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output logic lsu_c2_r_clk, // r pipe double pulse clock
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output logic lsu_store_c1_m_clk, // store in m
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output logic lsu_store_c1_r_clk, // store in r
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output logic lsu_stbuf_c1_clk,
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output logic lsu_bus_obuf_c1_clk, // ibuf clock
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output logic lsu_bus_ibuf_c1_clk, // ibuf clock
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output logic lsu_bus_buf_c1_clk, // ibuf clock
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output logic lsu_busm_clk, // bus clock
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output logic lsu_free_c2_clk,
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input logic scan_mode
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);
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logic lsu_c1_d_clken, lsu_c1_m_clken, lsu_c1_r_clken;
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logic lsu_c2_m_clken, lsu_c2_r_clken;
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logic lsu_c1_d_clken_q, lsu_c1_m_clken_q, lsu_c1_r_clken_q;
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logic lsu_store_c1_m_clken, lsu_store_c1_r_clken;
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logic lsu_stbuf_c1_clken;
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logic lsu_bus_ibuf_c1_clken, lsu_bus_obuf_c1_clken, lsu_bus_buf_c1_clken;
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logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
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//-------------------------------------------------------------------------------------------
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// Clock Enable logic
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//-------------------------------------------------------------------------------------------
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assign lsu_c1_d_clken = lsu_p.valid | dma_dccm_req | clk_override;
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assign lsu_c1_m_clken = lsu_pkt_d.valid | lsu_c1_d_clken_q | clk_override;
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assign lsu_c1_r_clken = lsu_pkt_m.valid | lsu_c1_m_clken_q | clk_override;
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assign lsu_c2_m_clken = lsu_c1_m_clken | lsu_c1_m_clken_q | clk_override;
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assign lsu_c2_r_clken = lsu_c1_r_clken | lsu_c1_r_clken_q | clk_override;
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assign lsu_store_c1_m_clken = ((lsu_c1_m_clken & lsu_pkt_d.store) | clk_override) ;
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assign lsu_store_c1_r_clken = ((lsu_c1_r_clken & lsu_pkt_m.store) | clk_override) ;
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assign lsu_stbuf_c1_clken = ldst_stbuf_reqvld_r | stbuf_reqvld_any | stbuf_reqvld_flushed_any | clk_override;
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assign lsu_bus_ibuf_c1_clken = lsu_busreq_r | clk_override;
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assign lsu_bus_obuf_c1_clken = (lsu_bus_buffer_pend_any | lsu_busreq_r | clk_override) & lsu_bus_clk_en;
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assign lsu_bus_buf_c1_clken = ~lsu_bus_buffer_empty_any | lsu_busreq_r | clk_override;
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assign lsu_free_c1_clken = (lsu_p.valid | lsu_pkt_d.valid | lsu_pkt_m.valid | lsu_pkt_r.valid) |
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~lsu_bus_buffer_empty_any | ~lsu_stbuf_empty_any | clk_override;
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assign lsu_free_c2_clken = lsu_free_c1_clken | lsu_free_c1_clken_q | clk_override;
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// Flops
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rvdff #(1) lsu_free_c1_clkenff (.din(lsu_free_c1_clken), .dout(lsu_free_c1_clken_q), .clk(free_clk), .*);
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rvdff #(1) lsu_c1_d_clkenff (.din(lsu_c1_d_clken), .dout(lsu_c1_d_clken_q), .clk(lsu_free_c2_clk), .*);
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rvdff #(1) lsu_c1_m_clkenff (.din(lsu_c1_m_clken), .dout(lsu_c1_m_clken_q), .clk(lsu_free_c2_clk), .*);
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rvdff #(1) lsu_c1_r_clkenff (.din(lsu_c1_r_clken), .dout(lsu_c1_r_clken_q), .clk(lsu_free_c2_clk), .*);
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// Clock Headers
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rvoclkhdr lsu_c1m_cgc ( .en(lsu_c1_m_clken), .l1clk(lsu_c1_m_clk), .* );
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rvoclkhdr lsu_c1r_cgc ( .en(lsu_c1_r_clken), .l1clk(lsu_c1_r_clk), .* );
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rvoclkhdr lsu_c2m_cgc ( .en(lsu_c2_m_clken), .l1clk(lsu_c2_m_clk), .* );
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rvoclkhdr lsu_c2r_cgc ( .en(lsu_c2_r_clken), .l1clk(lsu_c2_r_clk), .* );
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rvoclkhdr lsu_store_c1m_cgc (.en(lsu_store_c1_m_clken), .l1clk(lsu_store_c1_m_clk), .*);
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rvoclkhdr lsu_store_c1r_cgc (.en(lsu_store_c1_r_clken), .l1clk(lsu_store_c1_r_clk), .*);
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rvoclkhdr lsu_stbuf_c1_cgc ( .en(lsu_stbuf_c1_clken), .l1clk(lsu_stbuf_c1_clk), .* );
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rvoclkhdr lsu_bus_ibuf_c1_cgc ( .en(lsu_bus_ibuf_c1_clken), .l1clk(lsu_bus_ibuf_c1_clk), .* );
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rvclkhdr lsu_bus_obuf_c1_cgc ( .en(lsu_bus_obuf_c1_clken), .l1clk(lsu_bus_obuf_c1_clk), .* );
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rvoclkhdr lsu_bus_buf_c1_cgc ( .en(lsu_bus_buf_c1_clken), .l1clk(lsu_bus_buf_c1_clk), .* );
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rvclkhdr lsu_busm_cgc (.en(lsu_bus_clk_en), .l1clk(lsu_busm_clk), .*);
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rvoclkhdr lsu_free_cgc (.en(lsu_free_c2_clken), .l1clk(lsu_free_c2_clk), .*);
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endmodule
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