247 lines
9.5 KiB
Systemverilog
247 lines
9.5 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// el2_ifu_ifc_ctl.sv
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// Function: Fetch pipe control
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//
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// Comments:
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//********************************************************************************
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module el2_ifu_ifc_ctl
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import el2_pkg::*;
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#(
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`include "el2_param.vh"
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)
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(
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input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
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input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in.
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input logic rst_l, // reset enable, from core pin
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input logic scan_mode, // scan
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input logic ic_hit_f, // Icache hit
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input logic ifu_ic_mb_empty, // Miss buffer empty
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input logic ifu_fb_consume1, // Aligner consumed 1 fetch buffer
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input logic ifu_fb_consume2, // Aligner consumed 2 fetch buffers
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input logic dec_tlu_flush_noredir_wb, // Don't fetch on flush
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input logic exu_flush_final, // FLush
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input logic [31:1] exu_flush_path_final, // Flush path
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input logic ifu_bp_hit_taken_f, // btb hit, select the target path
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input logic [31:1] ifu_bp_btb_target_f, // predicted target PC
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input logic ic_dma_active, // IC DMA active, stop fetching
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input logic ic_write_stall, // IC is writing, stop fetching
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input logic dma_iccm_stall_any, // force a stall in the fetch pipe for DMA ICCM access
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input logic [31:0] dec_tlu_mrac_ff , // side_effect and cacheable for each region
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output logic [31:1] ifc_fetch_addr_f, // fetch addr F
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output logic [31:1] ifc_fetch_addr_bf, // fetch addr BF
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output logic ifc_fetch_req_f, // fetch request valid F
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output logic ifu_pmu_fetch_stall, // pmu event measuring fetch stall
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output logic ifc_fetch_uncacheable_bf, // The fetch request is uncacheable space. BF stage
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output logic ifc_fetch_req_bf, // Fetch request. Comes with the address. BF stage
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output logic ifc_fetch_req_bf_raw, // Fetch request without some qualifications. Used for clock-gating. BF stage
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output logic ifc_iccm_access_bf, // This request is to the ICCM. Do not generate misses to the bus.
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output logic ifc_region_acc_fault_bf, // Access fault. in ICCM region but offset is outside defined ICCM.
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output logic ifc_dma_access_ok // fetch is not accessing the ICCM, DMA can proceed
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);
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logic [31:1] fetch_addr_bf;
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logic [31:1] fetch_addr_next;
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logic [3:0] fb_write_f, fb_write_ns;
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logic fb_full_f_ns, fb_full_f;
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logic fb_right, fb_right2, fb_left, wfm, idle;
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logic sel_last_addr_bf, sel_next_addr_bf;
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logic miss_f, miss_a;
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logic flush_fb, dma_iccm_stall_any_f;
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logic mb_empty_mod, goto_idle, leave_idle;
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logic fetch_bf_en;
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logic line_wrap;
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logic fetch_addr_next_1;
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// FSM assignment
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typedef enum logic [1:0] { IDLE = 2'b00 ,
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FETCH = 2'b01 ,
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STALL = 2'b10 ,
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WFM = 2'b11 } state_t ;
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state_t state ;
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state_t next_state ;
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logic dma_stall;
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assign dma_stall = ic_dma_active | dma_iccm_stall_any_f;
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// Fetch address mux
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// - flush
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// - Miss *or* flush during WFM (icache miss buffer is blocking)
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// - Sequential
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if(pt.BTB_ENABLE==1) begin
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logic sel_btb_addr_bf;
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assign sel_last_addr_bf = ~exu_flush_final & (~ifc_fetch_req_f | ~ic_hit_f);
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assign sel_btb_addr_bf = ~exu_flush_final & ifc_fetch_req_f & ifu_bp_hit_taken_f & ic_hit_f;
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assign sel_next_addr_bf = ~exu_flush_final & ifc_fetch_req_f & ~ifu_bp_hit_taken_f & ic_hit_f;
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assign fetch_addr_bf[31:1] = ( ({31{exu_flush_final}} & exu_flush_path_final[31:1]) | // FLUSH path
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({31{sel_last_addr_bf}} & ifc_fetch_addr_f[31:1]) | // MISS path
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({31{sel_btb_addr_bf}} & {ifu_bp_btb_target_f[31:1]})| // BTB target
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({31{sel_next_addr_bf}} & {fetch_addr_next[31:1]})); // SEQ path
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end // if (pt.BTB_ENABLE=1)
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else begin
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assign sel_last_addr_bf = ~exu_flush_final & (~ifc_fetch_req_f | ~ic_hit_f);
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assign sel_next_addr_bf = ~exu_flush_final & ifc_fetch_req_f & ic_hit_f;
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assign fetch_addr_bf[31:1] = ( ({31{exu_flush_final}} & exu_flush_path_final[31:1]) | // FLUSH path
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({31{sel_last_addr_bf}} & ifc_fetch_addr_f[31:1]) | // MISS path
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({31{sel_next_addr_bf}} & {fetch_addr_next[31:1]})); // SEQ path
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end
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assign fetch_addr_next[31:1] = {({ifc_fetch_addr_f[31:2]} + 31'b1), fetch_addr_next_1 };
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assign line_wrap = (fetch_addr_next[pt.ICACHE_TAG_INDEX_LO] ^ ifc_fetch_addr_f[pt.ICACHE_TAG_INDEX_LO]);
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assign fetch_addr_next_1 = line_wrap ? 1'b0 : ifc_fetch_addr_f[1];
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assign ifc_fetch_req_bf_raw = ~idle;
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assign ifc_fetch_req_bf = ifc_fetch_req_bf_raw &
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~(fb_full_f_ns & ~(ifu_fb_consume2 | ifu_fb_consume1)) &
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~dma_stall &
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~ic_write_stall &
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~dec_tlu_flush_noredir_wb;
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assign fetch_bf_en = exu_flush_final | ifc_fetch_req_f;
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assign miss_f = ifc_fetch_req_f & ~ic_hit_f & ~exu_flush_final;
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assign mb_empty_mod = (ifu_ic_mb_empty | exu_flush_final) & ~dma_stall & ~miss_f & ~miss_a;
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// Halt flushes and takes us to IDLE
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assign goto_idle = exu_flush_final & dec_tlu_flush_noredir_wb;
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// If we're in IDLE, and we get a flush, goto FETCH
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assign leave_idle = exu_flush_final & ~dec_tlu_flush_noredir_wb & idle;
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//.i 7
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//.o 2
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//.ilb state[1] state[0] reset_delayed miss_f mb_empty_mod goto_idle leave_idle
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//.ob next_state[1] next_state[0]
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//.type fr
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//
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//# fetch 01, stall 10, wfm 11, idle 00
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//-- 1---- 01
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//-- 0--1- 00
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//00 0--00 00
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//00 0--01 01
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//
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//01 01-0- 11
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//01 00-0- 01
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//
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//11 0-10- 01
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//11 0-00- 11
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assign next_state[1] = (~state[1] & state[0] & miss_f & ~goto_idle) |
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(state[1] & ~mb_empty_mod & ~goto_idle);
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assign next_state[0] = (~goto_idle & leave_idle) | (state[0] & ~goto_idle);
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assign flush_fb = exu_flush_final;
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// model fb write logic to mass balance the fetch buffers
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assign fb_right = ( ifu_fb_consume1 & ~ifu_fb_consume2 & (~ifc_fetch_req_f | miss_f)) | // Consumed and no new fetch
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(ifu_fb_consume2 & ifc_fetch_req_f); // Consumed 2 and new fetch
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assign fb_right2 = (ifu_fb_consume2 & (~ifc_fetch_req_f | miss_f)); // Consumed 2 and no new fetch
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assign fb_left = ifc_fetch_req_f & ~(ifu_fb_consume1 | ifu_fb_consume2) & ~miss_f;
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// CBH
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assign fb_write_ns[3:0] = ( ({4{(flush_fb)}} & 4'b0001) |
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({4{~flush_fb & fb_right }} & {1'b0, fb_write_f[3:1]}) |
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({4{~flush_fb & fb_right2}} & {2'b0, fb_write_f[3:2]}) |
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({4{~flush_fb & fb_left }} & {fb_write_f[2:0], 1'b0}) |
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({4{~flush_fb & ~fb_right & ~fb_right2 & ~fb_left}} & fb_write_f[3:0]));
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assign fb_full_f_ns = fb_write_ns[3];
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assign idle = state == IDLE ;
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assign wfm = state == WFM ;
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rvdffie #(10) fbwrite_ff (.*, .clk(free_l2clk),
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.din( {dma_iccm_stall_any, miss_f, ifc_fetch_req_bf, next_state[1:0], fb_full_f_ns, fb_write_ns[3:0]}),
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.dout({dma_iccm_stall_any_f, miss_a, ifc_fetch_req_f, state[1:0], fb_full_f, fb_write_f[3:0]}));
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assign ifu_pmu_fetch_stall = wfm |
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(ifc_fetch_req_bf_raw &
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( (fb_full_f & ~(ifu_fb_consume2 | ifu_fb_consume1 | exu_flush_final)) |
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dma_stall));
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assign ifc_fetch_addr_bf[31:1] = fetch_addr_bf[31:1];
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rvdffpcie #(31) faddrf1_ff (.*, .en(fetch_bf_en), .din(fetch_addr_bf[31:1]), .dout(ifc_fetch_addr_f[31:1]));
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if (pt.ICCM_ENABLE) begin
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logic iccm_acc_in_region_bf;
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logic iccm_acc_in_range_bf;
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rvrangecheck #( .CCM_SADR (pt.ICCM_SADR),
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.CCM_SIZE (pt.ICCM_SIZE) ) iccm_rangecheck (
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.addr ({ifc_fetch_addr_bf[31:1],1'b0}) ,
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.in_range (iccm_acc_in_range_bf) ,
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.in_region(iccm_acc_in_region_bf)
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);
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assign ifc_iccm_access_bf = iccm_acc_in_range_bf ;
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assign ifc_dma_access_ok = ( (~ifc_iccm_access_bf |
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(fb_full_f & ~(ifu_fb_consume2 | ifu_fb_consume1)) |
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(wfm & ~ifc_fetch_req_bf) |
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idle ) & ~exu_flush_final) |
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dma_iccm_stall_any_f;
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assign ifc_region_acc_fault_bf = ~iccm_acc_in_range_bf & iccm_acc_in_region_bf ;
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end
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else begin
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assign ifc_iccm_access_bf = 1'b0 ;
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assign ifc_dma_access_ok = 1'b0 ;
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assign ifc_region_acc_fault_bf = 1'b0 ;
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end
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assign ifc_fetch_uncacheable_bf = ~dec_tlu_mrac_ff[{ifc_fetch_addr_bf[31:28] , 1'b0 }] ; // bit 0 of each region description is the cacheable bit
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endmodule // el2_ifu_ifc_ctl
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