11 lines
316 B
Systemverilog
11 lines
316 B
Systemverilog
// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
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// This is an automatically generated file by colin on Mon Mar 7 04:09:03 AM UTC 2022
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//
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// cmd: swerv -target=default -set build_axi4
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//
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`include "common_defines.vh"
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`undef RV_ASSERT_ON
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`undef TEC_RV_ICG
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`define RV_PHYSICAL 1
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