96 lines
3.1 KiB
Systemverilog
96 lines
3.1 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or it's affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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module el2_dec_gpr_ctl
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import el2_pkg::*;
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#(
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`include "el2_param.vh"
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) (
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input logic [4:0] raddr0, // logical read addresses
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input logic [4:0] raddr1,
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input logic wen0, // write enable
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input logic [4:0] waddr0, // write address
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input logic [31:0] wd0, // write data
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input logic wen1, // write enable
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input logic [4:0] waddr1, // write address
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input logic [31:0] wd1, // write data
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input logic wen2, // write enable
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input logic [4:0] waddr2, // write address
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input logic [31:0] wd2, // write data
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input logic clk,
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input logic rst_l,
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output logic [31:0] rd0, // read data
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output logic [31:0] rd1,
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input logic scan_mode
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);
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logic [31:1] [31:0] gpr_out; // 31 x 32 bit GPRs
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logic [31:1] [31:0] gpr_in;
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logic [31:1] w0v,w1v,w2v;
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logic [31:1] gpr_wr_en;
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// GPR Write Enables for power savings
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assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1] | w2v[31:1]);
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for ( genvar j=1; j<32; j++ ) begin : gpr
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rvdffe #(32) gprff (.*, .en(gpr_wr_en[j]), .din(gpr_in[j][31:0]), .dout(gpr_out[j][31:0]));
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end : gpr
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// the read out
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always_comb begin
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rd0[31:0] = 32'b0;
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rd1[31:0] = 32'b0;
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w0v[31:1] = 31'b0;
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w1v[31:1] = 31'b0;
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w2v[31:1] = 31'b0;
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gpr_in[31:1] = '0;
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// GPR Read logic
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for (int j=1; j<32; j++ ) begin
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rd0[31:0] |= ({32{(raddr0[4:0]== 5'(j))}} & gpr_out[j][31:0]);
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rd1[31:0] |= ({32{(raddr1[4:0]== 5'(j))}} & gpr_out[j][31:0]);
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end
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// GPR Write logic
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for (int j=1; j<32; j++ ) begin
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w0v[j] = wen0 & (waddr0[4:0]== 5'(j) );
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w1v[j] = wen1 & (waddr1[4:0]== 5'(j) );
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w2v[j] = wen2 & (waddr2[4:0]== 5'(j) );
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gpr_in[j] = ({32{w0v[j]}} & wd0[31:0]) |
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({32{w1v[j]}} & wd1[31:0]) |
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({32{w2v[j]}} & wd2[31:0]);
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end
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end // always_comb begin
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`ifdef ASSERT_ON
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logic write_collision_unused;
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assign write_collision_unused = ( (w0v[31:1] == w1v[31:1]) & wen0 & wen1 ) |
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( (w0v[31:1] == w2v[31:1]) & wen0 & wen2 ) |
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( (w1v[31:1] == w2v[31:1]) & wen1 & wen2 );
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// asserting that no 2 ports will write to the same gpr simultaneously
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assert_multiple_wen_to_same_gpr: assert #0 (~( write_collision_unused ) );
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`endif
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endmodule
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