447 lines
21 KiB
Systemverilog
447 lines
21 KiB
Systemverilog
// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// dec: decode unit - decode, bypassing, ARF, interrupts
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//
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//********************************************************************************
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// $Id$
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//
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//
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// Function: Decode
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// Comments: Decode, dependency scoreboard, ARF
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//
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//
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// A -> D -> EX1 ... WB
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//
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//********************************************************************************
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module el2_dec
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import el2_pkg::*;
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#(
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`include "el2_param.vh"
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)
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(
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input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
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input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
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input logic free_clk, // Clock always. Through two clock headers. For flops without second clock header built in.
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input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in.
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input logic lsu_fastint_stall_any, // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
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output logic dec_extint_stall, // Stall on external interrupt
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output logic dec_i0_decode_d, // Valid instruction at D-stage and not blocked
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output logic dec_pause_state_cg, // to top for active state clock gating
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output logic dec_tlu_core_empty,
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input logic rst_l, // reset, active low
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input logic [31:1] rst_vec, // reset vector, from core pins
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input logic nmi_int, // NMI pin
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input logic [31:1] nmi_vec, // NMI vector, from pins
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input logic i_cpu_halt_req, // Asynchronous Halt request to CPU
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input logic i_cpu_run_req, // Asynchronous Restart request to CPU
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output logic o_cpu_halt_status, // Halt status of core (pmu/fw)
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output logic o_cpu_halt_ack, // Halt request ack
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output logic o_cpu_run_ack, // Run request ack
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output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
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input logic [31:4] core_id, // CORE ID
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// external MPC halt/run interface
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input logic mpc_debug_halt_req, // Async halt request
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input logic mpc_debug_run_req, // Async run request
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input logic mpc_reset_run_req, // Run/halt after reset
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output logic mpc_debug_halt_ack, // Halt ack
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output logic mpc_debug_run_ack, // Run ack
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output logic debug_brkpt_status, // debug breakpoint
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input logic exu_pmu_i0_br_misp, // slot 0 branch misp
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input logic exu_pmu_i0_br_ataken, // slot 0 branch actual taken
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input logic exu_pmu_i0_pc4, // slot 0 4 byte branch
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input logic lsu_nonblock_load_valid_m, // valid nonblock load at m
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input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // -> corresponding tag
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input logic lsu_nonblock_load_inv_r, // invalidate request for nonblock load r
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input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // -> corresponding tag
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input logic lsu_nonblock_load_data_valid, // valid nonblock load data back
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input logic lsu_nonblock_load_data_error, // nonblock load bus error
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input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag
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input logic [31:0] lsu_nonblock_load_data, // nonblock load data
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input logic lsu_pmu_bus_trxn, // D side bus transaction
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input logic lsu_pmu_bus_misaligned, // D side bus misaligned
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input logic lsu_pmu_bus_error, // D side bus error
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input logic lsu_pmu_bus_busy, // D side bus busy
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input logic lsu_pmu_misaligned_m, // D side load or store misaligned
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input logic lsu_pmu_load_external_m, // D side bus load
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input logic lsu_pmu_store_external_m, // D side bus store
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input logic dma_pmu_dccm_read, // DMA DCCM read
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input logic dma_pmu_dccm_write, // DMA DCCM write
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input logic dma_pmu_any_read, // DMA read
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input logic dma_pmu_any_write, // DMA write
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input logic [31:1] lsu_fir_addr, // Fast int address
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input logic [1:0] lsu_fir_error, // Fast int lookup error
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input logic ifu_pmu_instr_aligned, // aligned instructions
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input logic ifu_pmu_fetch_stall, // fetch unit stalled
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input logic ifu_pmu_ic_miss, // icache miss
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input logic ifu_pmu_ic_hit, // icache hit
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input logic ifu_pmu_bus_error, // Instruction side bus error
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input logic ifu_pmu_bus_busy, // Instruction side bus busy
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input logic ifu_pmu_bus_trxn, // Instruction side bus transaction
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input logic ifu_ic_error_start, // IC single bit error
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input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error
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input logic [3:0] lsu_trigger_match_m,
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input logic dbg_cmd_valid, // debugger abstract command valid
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input logic dbg_cmd_write, // command is a write
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input logic [1:0] dbg_cmd_type, // command type
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input logic [31:0] dbg_cmd_addr, // command address
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input logic [1:0] dbg_cmd_wrdata, // command write data, for fence/fence_i
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input logic ifu_i0_icaf, // icache access fault
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input logic [1:0] ifu_i0_icaf_type, // icache access fault type
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input logic ifu_i0_icaf_second, // i0 has access fault on second 2B of 4B inst
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input logic ifu_i0_dbecc, // icache/iccm double-bit error
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input logic lsu_idle_any, // lsu idle for halting
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input el2_br_pkt_t i0_brp, // branch packet
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input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
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input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
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input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
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input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index
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input el2_lsu_error_pkt_t lsu_error_pkt_r, // LSU exception/error packet
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input logic lsu_single_ecc_error_incr, // LSU inc SB error counter
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input logic lsu_imprecise_error_load_any, // LSU imprecise load bus error
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input logic lsu_imprecise_error_store_any, // LSU imprecise store bus error
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input logic [31:0] lsu_imprecise_error_addr_any, // LSU imprecise bus error address
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input logic [31:0] exu_div_result, // final div result
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input logic exu_div_wren, // Divide write enable to GPR
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input logic [31:0] exu_csr_rs1_x, // rs1 for csr instruction
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input logic [31:0] lsu_result_m, // load result
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input logic [31:0] lsu_result_corr_r, // load result - corrected load data
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input logic lsu_load_stall_any, // This is for blocking loads
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input logic lsu_store_stall_any, // This is for blocking stores
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input logic dma_dccm_stall_any, // stall any load/store at decode, pmu event
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input logic dma_iccm_stall_any, // iccm stalled, pmu event
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input logic iccm_dma_sb_error, // ICCM DMA single bit error
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input logic exu_flush_final, // slot0 flush
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input logic [31:1] exu_npc_r, // next PC
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input logic [31:0] exu_i0_result_x, // alu result x
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input logic ifu_i0_valid, // fetch valids to instruction buffer
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input logic [31:0] ifu_i0_instr, // fetch inst's to instruction buffer
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input logic [31:1] ifu_i0_pc, // pc's for instruction buffer
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input logic ifu_i0_pc4, // indication of 4B or 2B for corresponding inst
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input logic [31:1] exu_i0_pc_x, // pc's for e1 from the alu's
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input logic mexintpend, // External interrupt pending
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input logic timer_int, // Timer interrupt pending (from pin)
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input logic soft_int, // Software interrupt pending (from pin)
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input logic [7:0] pic_claimid, // PIC claimid
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input logic [3:0] pic_pl, // PIC priv level
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input logic mhwakeup, // High priority wakeup
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output logic [3:0] dec_tlu_meicurpl, // to PIC, Current priv level
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output logic [3:0] dec_tlu_meipt, // to PIC
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input logic [70:0] ifu_ic_debug_rd_data, // diagnostic icache read data
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input logic ifu_ic_debug_rd_data_valid, // diagnostic icache read data valid
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output el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt, // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
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// Debug start
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input logic dbg_halt_req, // DM requests a halt
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input logic dbg_resume_req, // DM requests a resume
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input logic ifu_miss_state_idle, // I-side miss buffer empty
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output logic dec_tlu_dbg_halted, // Core is halted and ready for debug command
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output logic dec_tlu_debug_mode, // Core is in debug mode
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output logic dec_tlu_resume_ack, // Resume acknowledge
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output logic dec_tlu_flush_noredir_r, // Tell fetch to idle on this flush
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output logic dec_tlu_mpc_halted_only, // Core is halted only due to MPC
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output logic dec_tlu_flush_leak_one_r, // single step
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output logic dec_tlu_flush_err_r, // iside perr/ecc rfpc
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output logic [31:2] dec_tlu_meihap, // Fast ext int base
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output logic dec_debug_wdata_rs1_d, // insert debug write data into rs1 at decode
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output logic [31:0] dec_dbg_rddata, // debug command read data
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output logic dec_dbg_cmd_done, // abstract command is done
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output logic dec_dbg_cmd_fail, // abstract command failed (illegal reg address)
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output el2_trigger_pkt_t [3:0] trigger_pkt_any, // info needed by debug trigger blocks
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output logic dec_tlu_force_halt, // halt has been forced
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// Debug end
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// branch info from pipe0 for errors or counter updates
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input logic [1:0] exu_i0_br_hist_r, // history
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input logic exu_i0_br_error_r, // error
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input logic exu_i0_br_start_error_r, // start error
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input logic exu_i0_br_valid_r, // valid
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input logic exu_i0_br_mp_r, // mispredict
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input logic exu_i0_br_middle_r, // middle of bank
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// branch info from pipe1 for errors or counter updates
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input logic exu_i0_br_way_r, // way hit or repl
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output logic dec_i0_rs1_en_d, // Qualify GPR RS1 data
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output logic dec_i0_rs2_en_d, // Qualify GPR RS2 data
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output logic [31:0] gpr_i0_rs1_d, // gpr rs1 data
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output logic [31:0] gpr_i0_rs2_d, // gpr rs2 data
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output logic [31:0] dec_i0_immed_d, // immediate data
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output logic [12:1] dec_i0_br_immed_d, // br immediate data
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output el2_alu_pkt_t i0_ap, // alu packet
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output logic dec_i0_alu_decode_d, // schedule on D-stage alu
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output logic dec_i0_branch_d, // Branch in D-stage
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output logic dec_i0_select_pc_d, // select pc onto rs1 for jal's
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output logic [31:1] dec_i0_pc_d, // pc's at decode
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output logic [3:0] dec_i0_rs1_bypass_en_d, // rs1 bypass enable
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output logic [3:0] dec_i0_rs2_bypass_en_d, // rs2 bypass enable
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output logic [31:0] dec_i0_result_r, // Result R-stage
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output el2_lsu_pkt_t lsu_p, // lsu packet
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output logic dec_qual_lsu_d, // LSU instruction at D. Use to quiet LSU operands
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output el2_mul_pkt_t mul_p, // mul packet
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output el2_div_pkt_t div_p, // div packet
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output logic dec_div_cancel, // cancel divide operation
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output logic [11:0] dec_lsu_offset_d, // 12b offset for load/store addresses
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output logic dec_csr_ren_d, // CSR read enable
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output logic [31:0] dec_csr_rddata_d, // CSR read data
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output logic dec_tlu_flush_lower_r, // tlu flush due to late mp, exception, rfpc, or int
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output logic dec_tlu_flush_lower_wb,
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output logic [31:1] dec_tlu_flush_path_r, // tlu flush target
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output logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state
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output logic dec_tlu_fence_i_r, // flush is a fence_i rfnpc, flush icache
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output logic [31:1] pred_correct_npc_x, // npc if prediction is correct at e2 stage
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output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot 0 branch predictor update packet
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output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
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output logic dec_tlu_perfcnt1, // toggles when slot0 perf counter 1 has an event inc
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output logic dec_tlu_perfcnt2, // toggles when slot0 perf counter 2 has an event inc
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output logic dec_tlu_perfcnt3, // toggles when slot0 perf counter 3 has an event inc
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output el2_predict_pkt_t dec_i0_predict_p_d, // prediction packet to alus
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output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // DEC predict fghr
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output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // DEC predict index
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output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // DEC predict branch tag
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output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
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output logic dec_lsu_valid_raw_d,
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output logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control
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output logic [1:0] dec_data_en, // clock-gate control logic
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output logic [1:0] dec_ctl_en,
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input logic [15:0] ifu_i0_cinst, // 16b compressed instruction
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output el2_trace_pkt_t trace_rv_trace_pkt, // trace packet
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// feature disable from mfdc
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output logic dec_tlu_external_ldfwd_disable, // disable external load forwarding
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output logic dec_tlu_sideeffect_posted_disable, // disable posted stores to side-effect address
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output logic dec_tlu_core_ecc_disable, // disable core ECC
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output logic dec_tlu_bpred_disable, // disable branch prediction
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output logic dec_tlu_wb_coalescing_disable, // disable writebuffer coalescing
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output logic [2:0] dec_tlu_dma_qos_prty, // DMA QoS priority coming from MFDC [18:16]
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// clock gating overrides from mcgc
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output logic dec_tlu_misc_clk_override, // override misc clock domain gating
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output logic dec_tlu_ifu_clk_override, // override fetch clock domain gating
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output logic dec_tlu_lsu_clk_override, // override load/store clock domain gating
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output logic dec_tlu_bus_clk_override, // override bus clock domain gating
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output logic dec_tlu_pic_clk_override, // override PIC clock domain gating
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output logic dec_tlu_picio_clk_override, // override PICIO clock domain gating
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output logic dec_tlu_dccm_clk_override, // override DCCM clock domain gating
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output logic dec_tlu_icm_clk_override, // override ICCM clock domain gating
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output logic dec_tlu_i0_commit_cmt, // committed i0 instruction
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input logic scan_mode // Flop scan mode control
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);
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logic dec_tlu_dec_clk_override; // to and from dec blocks
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logic clk_override;
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logic dec_ib0_valid_d;
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logic dec_pmu_instr_decoded;
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logic dec_pmu_decode_stall;
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logic dec_pmu_presync_stall;
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logic dec_pmu_postsync_stall;
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logic dec_tlu_wr_pause_r; // CSR write to pause reg is at R.
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logic [4:0] dec_i0_rs1_d;
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logic [4:0] dec_i0_rs2_d;
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logic [31:0] dec_i0_instr_d;
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logic dec_tlu_trace_disable;
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logic dec_tlu_pipelining_disable;
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logic [4:0] dec_i0_waddr_r;
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logic dec_i0_wen_r;
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logic [31:0] dec_i0_wdata_r;
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logic dec_csr_wen_r; // csr write enable at wb
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logic [11:0] dec_csr_wraddr_r; // write address for csryes
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logic [31:0] dec_csr_wrdata_r; // csr write data at wb
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logic [11:0] dec_csr_rdaddr_d; // read address for csr
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logic dec_csr_legal_d; // csr indicates legal operation
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logic dec_csr_wen_unq_d; // valid csr with write - for csr legal
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logic dec_csr_any_unq_d; // valid csr - for csr legal
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logic dec_csr_stall_int_ff; // csr is mie/mstatus
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el2_trap_pkt_t dec_tlu_packet_r;
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logic dec_i0_pc4_d;
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logic dec_tlu_presync_d;
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logic dec_tlu_postsync_d;
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logic dec_tlu_debug_stall;
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logic [31:0] dec_illegal_inst;
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logic dec_i0_icaf_d;
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logic dec_i0_dbecc_d;
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logic dec_i0_icaf_second_d;
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logic [3:0] dec_i0_trigger_match_d;
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logic dec_debug_fence_d;
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logic dec_nonblock_load_wen;
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logic [4:0] dec_nonblock_load_waddr;
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logic dec_tlu_flush_pause_r;
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el2_br_pkt_t dec_i0_brp;
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logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index;
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logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr;
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logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag;
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logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index; // Fully associt btb index
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logic [31:1] dec_tlu_i0_pc_r;
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logic dec_tlu_i0_kill_writeb_wb;
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logic dec_tlu_i0_valid_r;
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logic dec_pause_state;
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logic [1:0] dec_i0_icaf_type_d; // i0 instruction access fault type
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logic dec_tlu_flush_extint; // Fast ext int started
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logic [31:0] dec_i0_inst_wb;
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logic [31:1] dec_i0_pc_wb;
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logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1;
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logic [4:0] dec_tlu_exc_cause_wb1;
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logic [31:0] dec_tlu_mtval_wb1;
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logic dec_tlu_i0_exc_valid_wb1;
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logic [4:0] div_waddr_wb;
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logic dec_div_active;
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logic dec_debug_valid_d;
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assign clk_override = dec_tlu_dec_clk_override;
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assign dec_dbg_rddata[31:0] = dec_i0_wdata_r[31:0];
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el2_dec_ib_ctl #(.pt(pt)) instbuff (.*);
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el2_dec_decode_ctl #(.pt(pt)) decode (.*);
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el2_dec_tlu_ctl #(.pt(pt)) tlu (.*);
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el2_dec_gpr_ctl #(.pt(pt)) arf (.*,
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// inputs
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.raddr0(dec_i0_rs1_d[4:0]),
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.raddr1(dec_i0_rs2_d[4:0]),
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.wen0(dec_i0_wen_r), .waddr0(dec_i0_waddr_r[4:0]), .wd0(dec_i0_wdata_r[31:0]),
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.wen1(dec_nonblock_load_wen), .waddr1(dec_nonblock_load_waddr[4:0]), .wd1(lsu_nonblock_load_data[31:0]),
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.wen2(exu_div_wren), .waddr2(div_waddr_wb), .wd2(exu_div_result[31:0]),
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// outputs
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.rd0(gpr_i0_rs1_d[31:0]), .rd1(gpr_i0_rs2_d[31:0])
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);
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// Trigger
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el2_dec_trigger #(.pt(pt)) dec_trigger (.*);
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// trace
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assign trace_rv_trace_pkt.trace_rv_i_insn_ip = dec_i0_inst_wb[31:0];
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assign trace_rv_trace_pkt.trace_rv_i_address_ip = { dec_i0_pc_wb[31:1], 1'b0};
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assign trace_rv_trace_pkt.trace_rv_i_valid_ip = dec_tlu_int_valid_wb1 | dec_tlu_i0_valid_wb1 | dec_tlu_i0_exc_valid_wb1;
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assign trace_rv_trace_pkt.trace_rv_i_exception_ip = dec_tlu_int_valid_wb1 | dec_tlu_i0_exc_valid_wb1;
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assign trace_rv_trace_pkt.trace_rv_i_ecause_ip = dec_tlu_exc_cause_wb1[4:0]; // replicate across ports
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assign trace_rv_trace_pkt.trace_rv_i_interrupt_ip = dec_tlu_int_valid_wb1;
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assign trace_rv_trace_pkt.trace_rv_i_tval_ip = dec_tlu_mtval_wb1[31:0]; // replicate across ports
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// end trace
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endmodule // el2_dec
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