Merge remote-tracking branch 'upstream/master' into shapeinference-pad
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chentong
commit
ec43fadc3b
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@ -111,6 +111,7 @@ def ONNXGemmNoBiasOp: ONNX_Op<"GemmNoBias",
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def ONNXConvNoBiasOp:ONNX_Op<"ConvNoBias",
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[NoSideEffect, DeclareOpInterfaceMethods<ShapeInferenceOpInterface>]> {
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let hasCanonicalizer = 1;
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let summary = "ONNX Conv operation with no Bias operand.";
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let description = [{
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"The convolution operator consumes an input tensor and a filter, and"
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@ -39,14 +39,14 @@ def GemmTransB : NativeCodeCall<"$_builder.getI64IntegerAttr(0)">;
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// onnx.add(onnx.matmul(%X, %Y), %Z) = onnx.Gemm(%X, %Y, %Z)
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def MulAddToGemmOptPattern : Pat<(ONNXAddOp (ONNXMatMulOp:$res $m1, $m2), $m3),
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(ONNXGemmOp $m1, $m2, $m3, (GemmAlpha), (GemmBeta), (GemmTransA), (GemmTransB)),
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[(HasOneUse $res), (HasRankOf<2> $m1), (HasRankOf<2> $m2)]>;
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[(HasOneUse $res), (HasRankOf<2> $m1), (HasRankOf<2> $m2)]>;
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// ONNX_Op (onnx.Identity (%X)) = ONNX_Op (%X)
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def IdentityEliminationPattern : Pat<(ONNXIdentityOp $arg),
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(replaceWithValue $arg)>;
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(replaceWithValue $arg)>;
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def ConstantPadPattern : Pat<(ONNXPadConstantValueOp $m1, (ONNXConstantOp:$res $v1, $v2), $m2, $m3),
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(ONNXPadConstantValuePadOp $m1, $v2, $m2, $m3),
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[(HasOneUse $res)]>;
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[(HasOneUse $res)]>;
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#endif // ONNX_COMBINE
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@ -263,6 +263,103 @@ struct ReduceSumSquareOpPattern : public RewritePattern {
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return matchSuccess();
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};
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};
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//===----------------------------------------------------------------------===//
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// Rewrite:
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// %0 = onnx.ConvNoBiasOp(%D : tensor<DShape>, %K)
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// {pads = [b0, b1, ... bK, e0, e1, ..., eK]} ->
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// tensor<OutShape>
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//
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// as:
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// %0 = onnx.PadConstantValuePasOp(%D)
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// {pads = [0, 0, b0, b1, ... bK, 0, 0, e0, e1, ..., eK]} ->
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// tensor<DPaddedShape>
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// %1 = onnx.ConvNoBias(%0 : tensor<DPaddedShape>, %K) {pads = [0, ..., 0]} ->
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// tensor<OutShape>
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//===----------------------------------------------------------------------===//
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struct SplitConvOpPattern : public RewritePattern {
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SplitConvOpPattern(MLIRContext *context)
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: RewritePattern(ONNXConvNoBiasOp::getOperationName(),
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{ONNXPadConstantValuePadOp::getOperationName(),
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ONNXConvNoBiasOp::getOperationName()},
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1, context) {}
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PatternMatchResult matchAndRewrite(Operation *op,
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PatternRewriter &rewriter) const override {
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auto loc = op->getLoc();
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// If convolution does not use padding then no rewrite is required.
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ONNXConvNoBiasOp convOp = llvm::dyn_cast<ONNXConvNoBiasOp>(op);
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auto padsAttribute = convOp.padsAttr();
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if (!padsAttribute)
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return matchFailure();
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// If auto_pad is VALID then no padding happens and no rewrite isrequired.
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auto autoPad = convOp.auto_pad();
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if (autoPad == "VALID")
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return matchFailure();
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auto data = op->getOperands()[0];
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auto inputShape = data.getType().cast<TensorType>().getShape();
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// Dimensionality of the input:
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// inputRank
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// |----------------------|
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// D : (N x C x D1 x D2 x ... DK)
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// |______________|
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// inputDims
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//
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int64_t inputRank = inputShape.size();
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int64_t inputDims = inputRank - 2;
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// If all pads values are equal to zero then no rewrite is required.
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bool allZeros = true;
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for (auto padsValue : padsAttribute.getValue()) {
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if (padsValue.cast<IntegerAttr>().getInt() > 0) {
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allZeros = false;
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break;
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}
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}
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if (allZeros)
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return matchFailure();
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// Create padding vector for the explicit padding op attribute.
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SmallVector<int64_t, 4> pads(2 * inputRank, 0);
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SmallVector<int64_t, 4> outPaddedShape(inputRank, 0);
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outPaddedShape[0] = inputShape[0];
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outPaddedShape[1] = inputShape[1];
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for (int i = 0; i < inputDims; ++i) {
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int64_t beginPad =
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padsAttribute.getValue()[i].cast<IntegerAttr>().getInt();
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int64_t endPad =
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padsAttribute.getValue()[inputDims + i].cast<IntegerAttr>().getInt();
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pads[i + 2] = beginPad;
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pads[inputRank + i + 2] = endPad;
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outPaddedShape[i + 2] += beginPad + inputShape[i + 2] + endPad;
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}
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// Create padding operation.
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auto inputElemType = data.getType().cast<TensorType>().getElementType();
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ONNXPadConstantValuePadOp paddingOp =
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rewriter.create<ONNXPadConstantValuePadOp>(
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loc, RankedTensorType::get(outPaddedShape, inputElemType), data,
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rewriter.getI64ArrayAttr(pads), FloatAttr::get(inputElemType, 0),
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StringAttr::get("constant", loc->getContext()));
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SmallVector<int64_t, 4> newConvPads(2 * inputDims, 0);
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auto tensorType = (*op->result_type_begin()).cast<TensorType>();
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ONNXConvNoBiasOp newConvOp = rewriter.create<ONNXConvNoBiasOp>(
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loc, tensorType, paddingOp.getResult(), convOp.getOperands()[1],
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convOp.auto_padAttr(), convOp.dilationsAttr(),
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convOp.groupAttr(), convOp.kernel_shapeAttr(),
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rewriter.getI64ArrayAttr(newConvPads),
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convOp.stridesAttr());
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rewriter.replaceOp(op, newConvOp.getResult());
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return matchSuccess();
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};
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};
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} // end anonymous namespace
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/// on the ONNXReduceL1Op.
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@ -293,3 +390,9 @@ void ONNXReduceSumSquareOp::getCanonicalizationPatterns(
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OwningRewritePatternList &results, MLIRContext *context) {
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results.insert<ReduceSumSquareOpPattern>(context);
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}
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/// on the ONNXReduceSumSquareOp.
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void ONNXConvNoBiasOp::getCanonicalizationPatterns(
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OwningRewritePatternList &results, MLIRContext *context) {
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results.insert<SplitConvOpPattern>(context);
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}
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@ -92,3 +92,12 @@ func @test_constant_pad(%arg0 : tensor<?x?xf32>) -> tensor<*xf32> {
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%2 = "onnx.PadConstantValue"(%arg0, %0) {constant_value=0. : f32, mode = "constant"} : (tensor<?x?xf32>, tensor<?xi64>)-> tensor<*xf32>
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"std.return"(%2) : (tensor<*xf32>) -> ()
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}
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// CHECK-LABEL: @test_conv_split(%{{.*}}: tensor<1x9x32x64xf32>, %{{.*}}: tensor<5x9x6x7xf32>) -> tensor<*xf32> {
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func @test_conv_split(%arg0 : tensor<1x9x32x64xf32>, %arg1 : tensor<5x9x6x7xf32>) -> tensor<*xf32> {
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%0 = "onnx.ConvNoBias"(%arg0, %arg1) {auto_pad = "NOTSET", group = 1 : i64, pads = [2, 3, 4, 5]} : (tensor<1x9x32x64xf32>, tensor<5x9x6x7xf32>) -> tensor<*xf32>
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"std.return"(%0) : (tensor<*xf32>) -> ()
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// CHECK-NEXT: %0 = "onnx.PadConstatValuePad"(%arg0) {constant_value = 0.000000e+00 : f32, mode = "constant", pads = [0, 0, 2, 3, 0, 0, 4, 5]} : (tensor<1x9x32x64xf32>) -> tensor<1x9x38x72xf32>
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// CHECK-NEXT: %1 = "onnx.ConvNoBias"(%0, %arg1) {auto_pad = "NOTSET", group = 1 : i64, pads = [0, 0, 0, 0]} : (tensor<1x9x38x72xf32>, tensor<5x9x6x7xf32>) -> tensor<*xf32>
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// CHECK-NEXT: return %1 : tensor<*xf32>
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}
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