2015-06-09 18:45:45 +08:00
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read_verilog ../../picorv32.v
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read_xdc synth_area.xdc
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2015-06-26 16:46:51 +08:00
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synth_design -part xc7a15t-fgg484 -top picorv32_axi
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2015-06-09 18:45:45 +08:00
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opt_design
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place_design
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route_design
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report_utilization
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report_timing
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write_verilog -force synth_area.v
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