picorv32/scripts/vivado/synth_speed.tcl

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Tcl
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2015-06-09 18:45:45 +08:00
read_verilog ../../picorv32.v
read_xdc synth_speed.xdc
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synth_design -part xc7k70t-fbg676 -top picorv32_axi
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opt_design
place_design
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phys_opt_design
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route_design
report_utilization
report_timing
write_verilog -force synth_speed.v