picorv32/scripts/vivado/synth_soc.tcl

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Tcl
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2015-06-09 18:45:45 +08:00
read_verilog soc_top.v
read_verilog ../../picorv32.v
read_xdc synth_soc.xdc
synth_design -part xc7a15t-csg324 -top soc_top
opt_design
place_design
route_design
report_utilization
report_timing
write_verilog -force synth_soc.v