2015-06-30 07:46:25 +08:00
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# yosys synthesis script for post-synthesis simulation (make test_synth)
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read_verilog picorv32.v
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2016-12-15 19:48:57 +08:00
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chparam -set COMPRESSED_ISA 1 -set ENABLE_MUL 1 -set ENABLE_DIV 1 \
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-set ENABLE_IRQ 1 -set ENABLE_TRACE 1 picorv32_axi
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2015-06-30 07:46:25 +08:00
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hierarchy -top picorv32_axi
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synth
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write_verilog synth.v
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