96 lines
2.2 KiB
Coq
96 lines
2.2 KiB
Coq
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`timescale 1 ns / 1 ps
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`undef VERBOSE_MEM
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`undef WRITE_VCD
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module testbench;
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reg clk = 1;
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reg resetn = 0;
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wire trap;
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always #5 clk = ~clk;
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initial begin
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repeat (100) @(posedge clk);
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resetn <= 1;
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end
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wire mem_valid;
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wire mem_instr;
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reg mem_ready;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [3:0] mem_wstrb;
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reg [31:0] mem_rdata;
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picorv32 uut (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata )
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);
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localparam MEM_SIZE = 4*1024*1024;
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reg [7:0] memory [0:MEM_SIZE-1];
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initial $readmemh("firmware.hex", memory);
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always @(posedge clk) begin
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mem_ready <= 0;
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if (mem_valid && !mem_ready) begin
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mem_ready <= 1;
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mem_rdata <= 'bx;
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case (1)
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mem_addr < MEM_SIZE: begin
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if (|mem_wstrb) begin
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if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24];
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end else begin
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mem_rdata <= {memory[mem_addr+3], memory[mem_addr+2], memory[mem_addr+1], memory[mem_addr]};
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end
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end
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mem_addr == 32'h 1000_0000: begin
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$write("%c", mem_wdata[7:0]);
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end
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endcase
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end
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if (mem_valid && mem_ready) begin
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`ifdef VERBOSE_MEM
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if (|mem_wstrb)
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$display("WR: ADDR=%x DATA=%x MASK=%b", mem_addr, mem_wdata, mem_wstrb);
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else
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$display("RD: ADDR=%x DATA=%x%s", mem_addr, mem_rdata, mem_instr ? " INSN" : "");
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`endif
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if (^mem_addr === 1'bx ||
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(mem_wstrb[0] && ^mem_wdata[ 7: 0] == 1'bx) ||
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(mem_wstrb[1] && ^mem_wdata[15: 8] == 1'bx) ||
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(mem_wstrb[2] && ^mem_wdata[23:16] == 1'bx) ||
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(mem_wstrb[3] && ^mem_wdata[31:24] == 1'bx)) begin
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$display("CRITICAL UNDEF MEM TRANSACTION");
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$finish;
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end
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end
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end
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`ifdef WRITE_VCD
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initial begin
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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end
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`endif
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always @(posedge clk) begin
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if (resetn && trap) begin
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repeat (10) @(posedge clk);
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$display("TRAP");
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$finish;
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end
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end
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endmodule
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