2015-07-02 03:51:15 +08:00
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read_verilog ../../picorv32.v
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read_verilog synth_area_top.v
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read_xdc synth_area.xdc
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2015-07-02 04:18:20 +08:00
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synth_design -part xc7k70t-fbg676 -top top_regular
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2015-07-02 03:51:15 +08:00
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opt_design -resynth_seq_area
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report_utilization
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# report_timing
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