picorv32/scripts/vivado/synth_area_large.tcl

read_verilog ../../picorv32.v
read_verilog synth_area_top.v
read_xdc synth_area.xdc

synth_design -part xc7k70t-fbg676 -top top_large
opt_design -resynth_seq_area

report_utilization
# report_timing
Added vivado synth_area_{small,regular,large}.tcl scripts 2015-07-02 03:51:15 +08:00			`read_verilog ../../picorv32.v`
Vivado 2015.2 area evaluation 2015-07-02 04:18:20 +08:00			`read_verilog synth_area_top.v`
Added vivado synth_area_{small,regular,large}.tcl scripts 2015-07-02 03:51:15 +08:00			`read_xdc synth_area.xdc`

Vivado 2015.2 area evaluation 2015-07-02 04:18:20 +08:00			`synth_design -part xc7k70t-fbg676 -top top_large`
Added vivado synth_area_{small,regular,large}.tcl scripts 2015-07-02 03:51:15 +08:00			`opt_design -resynth_seq_area`

			`report_utilization`
			`# report_timing`