2015-06-06 20:01:37 +08:00
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# vivado -nojournal -log synth_vivado.log -mode batch -source synth_vivado.tcl
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2015-06-07 02:14:58 +08:00
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read_verilog synth_vivado_soc.v
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read_verilog ../picorv32.v
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2015-06-06 20:01:37 +08:00
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read_xdc synth_vivado.xdc
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synth_design -part xc7a15t-csg324 -top picorv32_axi
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2015-06-07 02:14:58 +08:00
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# synth_design -part xc7a15t-csg324 -top test_soc
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2015-06-06 20:01:37 +08:00
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opt_design
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place_design
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route_design
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report_utilization
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report_timing
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2015-06-07 02:14:58 +08:00
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write_verilog -force synth_vivado_syn.v
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2015-06-06 20:01:37 +08:00
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