17 lines
489 B
Diff
17 lines
489 B
Diff
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diff --git a/riscv/processor.cc b/riscv/processor.cc
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index 3b834c5..e112029 100644
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--- a/riscv/processor.cc
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+++ b/riscv/processor.cc
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@@ -201,9 +201,10 @@ void processor_t::set_privilege(reg_t prv)
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void processor_t::take_trap(trap_t& t, reg_t epc)
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{
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- if (debug)
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+ // if (debug)
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fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
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id, t.name(), epc);
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+ exit(1);
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// by default, trap to M-mode, unless delegated to S-mode
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reg_t bit = t.cause();
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