Added ENABLE_DIV and picorv32_pcpi_div
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11
README.md
11
README.md
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@ -67,8 +67,9 @@ fault handlers, or catch instructions from a larger ISA and emulate them in
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software.
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The optional Pico Co-Processor Interface (PCPI) can be used to implement
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non-branching instructions in an external coprocessor. An implementation
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of a core that implements the `MUL[H[SU|U]]` instructions is provided.
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non-branching instructions in an external coprocessor. Implementations
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of PCPI cores that implement the M Standard Extension instructions
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`MUL[H[SU|U]]` and `DIV[U]/REM[U]` are included in this package.
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Files in this Repository
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@ -209,6 +210,12 @@ This parameter internally enables PCPI and instantiates the `picorv32_pcpi_mul`
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core that implements the `MUL[H[SU|U]]` instructions. The external PCPI
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interface only becomes functional when ENABLE_PCPI is set as well.
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#### ENABLE_DIV (default = 0)
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This parameter internally enables PCPI and instantiates the `picorv32_pcpi_div`
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core that implements the `DIV[U]/REM[U]` instructions. The external PCPI
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interface only becomes functional when ENABLE_PCPI is set as well.
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#### ENABLE_IRQ (default = 0)
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Set this to 1 to enable IRQs. (see "Custom Instructions for IRQ Handling" below
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@ -435,6 +435,11 @@ start:
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TEST(mulhu)
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TEST(mul)
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TEST(div)
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TEST(divu)
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TEST(rem)
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TEST(remu)
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TEST(simple)
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/* set stack pointer */
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122
picorv32.v
122
picorv32.v
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@ -50,6 +50,7 @@ module picorv32 #(
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parameter [ 0:0] CATCH_ILLINSN = 1,
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parameter [ 0:0] ENABLE_PCPI = 0,
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parameter [ 0:0] ENABLE_MUL = 0,
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parameter [ 0:0] ENABLE_DIV = 0,
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parameter [ 0:0] ENABLE_IRQ = 0,
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parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
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parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
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@ -99,7 +100,7 @@ module picorv32 #(
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localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
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localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
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localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL;
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localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_DIV;
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reg [63:0] count_cycle, count_instr;
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reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
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@ -127,6 +128,11 @@ module picorv32 #(
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wire pcpi_mul_wait;
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wire pcpi_mul_ready;
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wire pcpi_div_wr;
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wire [31:0] pcpi_div_rd;
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wire pcpi_div_wait;
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wire pcpi_div_ready;
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reg pcpi_int_wr;
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reg [31:0] pcpi_int_rd;
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reg pcpi_int_wait;
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@ -152,11 +158,31 @@ module picorv32 #(
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assign pcpi_mul_ready = 0;
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end endgenerate
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generate if (ENABLE_DIV) begin
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picorv32_pcpi_div pcpi_div (
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.clk (clk ),
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.resetn (resetn ),
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.pcpi_valid(pcpi_valid ),
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.pcpi_insn (pcpi_insn ),
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.pcpi_rs1 (pcpi_rs1 ),
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.pcpi_rs2 (pcpi_rs2 ),
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.pcpi_wr (pcpi_div_wr ),
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.pcpi_rd (pcpi_div_rd ),
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.pcpi_wait (pcpi_div_wait ),
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.pcpi_ready(pcpi_div_ready )
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);
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end else begin
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assign pcpi_div_wr = 0;
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assign pcpi_div_rd = 1'bx;
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assign pcpi_div_wait = 0;
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assign pcpi_div_ready = 0;
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end endgenerate
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always @* begin
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pcpi_int_wr = 0;
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pcpi_int_rd = 1'bx;
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pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, ENABLE_MUL && pcpi_mul_wait};
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pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, ENABLE_MUL && pcpi_mul_ready};
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pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, ENABLE_MUL && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait};
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pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, ENABLE_MUL && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
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(* parallel_case *)
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case (1'b1)
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@ -168,6 +194,10 @@ module picorv32 #(
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pcpi_int_wr = pcpi_mul_wr;
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pcpi_int_rd = pcpi_mul_rd;
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end
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ENABLE_DIV && pcpi_div_ready: begin
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pcpi_int_wr = pcpi_div_wr;
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pcpi_int_rd = pcpi_div_rd;
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end
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endcase
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end
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@ -1548,6 +1578,90 @@ module picorv32_pcpi_mul #(
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endmodule
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/***************************************************************
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* picorv32_pcpi_div
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***************************************************************/
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module picorv32_pcpi_div (
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input clk, resetn,
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input pcpi_valid,
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input [31:0] pcpi_insn,
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input [31:0] pcpi_rs1,
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input [31:0] pcpi_rs2,
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output reg pcpi_wr,
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output reg [31:0] pcpi_rd,
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output reg pcpi_wait,
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output reg pcpi_ready
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);
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reg instr_div, instr_divu, instr_rem, instr_remu;
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wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};
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reg pcpi_wait_q;
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wire start = pcpi_wait && !pcpi_wait_q;
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always @(posedge clk) begin
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instr_div <= 0;
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instr_divu <= 0;
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instr_rem <= 0;
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instr_remu <= 0;
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if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
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case (pcpi_insn[14:12])
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3'b100: instr_div <= 1;
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3'b101: instr_divu <= 1;
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3'b110: instr_rem <= 1;
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3'b111: instr_remu <= 1;
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endcase
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end
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pcpi_wait <= instr_any_div_rem;
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pcpi_wait_q <= pcpi_wait;
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end
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reg [31:0] dividend;
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reg [62:0] divisor;
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reg [31:0] quotient;
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reg [31:0] quotient_msk;
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reg running;
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reg outsign;
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always @(posedge clk) begin
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pcpi_ready <= 0;
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pcpi_wr <= 0;
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pcpi_rd <= 'bx;
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if (!resetn) begin
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running <= 0;
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end else
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if (start) begin
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running <= 1;
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dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
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divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
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outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31])) || (instr_rem && pcpi_rs1[31]);
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quotient <= 0;
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quotient_msk <= 1 << 31;
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end else
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if (!quotient_msk && running) begin
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running <= 0;
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pcpi_ready <= 1;
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pcpi_wr <= 1;
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if (instr_div || instr_divu)
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pcpi_rd <= outsign ? -quotient : quotient;
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else
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pcpi_rd <= outsign ? -dividend : dividend;
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end else begin
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if (divisor <= dividend) begin
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dividend <= dividend - divisor;
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quotient <= quotient | quotient_msk;
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end
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divisor <= divisor >> 1;
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quotient_msk <= quotient_msk >> 1;
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end
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end
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endmodule
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/***************************************************************
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* picorv32_axi
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***************************************************************/
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@ -1564,6 +1678,7 @@ module picorv32_axi #(
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parameter [ 0:0] CATCH_ILLINSN = 1,
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parameter [ 0:0] ENABLE_PCPI = 0,
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parameter [ 0:0] ENABLE_MUL = 0,
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parameter [ 0:0] ENABLE_DIV = 0,
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parameter [ 0:0] ENABLE_IRQ = 0,
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parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
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parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
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@ -1662,6 +1777,7 @@ module picorv32_axi #(
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.CATCH_ILLINSN (CATCH_ILLINSN ),
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.ENABLE_PCPI (ENABLE_PCPI ),
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.ENABLE_MUL (ENABLE_MUL ),
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.ENABLE_DIV (ENABLE_DIV ),
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.ENABLE_IRQ (ENABLE_IRQ ),
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.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
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.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
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@ -118,6 +118,7 @@ module picorv32_wrapper #(
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.COMPRESSED_ISA(1),
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`endif
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.ENABLE_MUL(1),
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.ENABLE_DIV(1),
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.ENABLE_IRQ(1)
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) uut (
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.clk (clk ),
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@ -0,0 +1,41 @@
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# See LICENSE for license details.
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#*****************************************************************************
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# div.S
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#-----------------------------------------------------------------------------
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#
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# Test div instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Arithmetic tests
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#-------------------------------------------------------------
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TEST_RR_OP( 2, div, 3, 20, 6 );
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TEST_RR_OP( 3, div, -3, -20, 6 );
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TEST_RR_OP( 4, div, -3, 20, -6 );
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TEST_RR_OP( 5, div, 3, -20, -6 );
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TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 );
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TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 );
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TEST_RR_OP( 8, div, -1, -1<<63, 0 );
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TEST_RR_OP( 9, div, -1, 1, 0 );
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TEST_RR_OP(10, div, -1, 0, 0 );
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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@ -0,0 +1,41 @@
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# See LICENSE for license details.
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#*****************************************************************************
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# divu.S
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#-----------------------------------------------------------------------------
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#
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# Test divu instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Arithmetic tests
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#-------------------------------------------------------------
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TEST_RR_OP( 2, divu, 3, 20, 6 );
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TEST_RR_OP( 3, divu, 715827879, -20, 6 );
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TEST_RR_OP( 4, divu, 0, 20, -6 );
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TEST_RR_OP( 5, divu, 0, -20, -6 );
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TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 );
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TEST_RR_OP( 7, divu, 0, -1<<31, -1 );
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TEST_RR_OP( 8, divu, -1, -1<<31, 0 );
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TEST_RR_OP( 9, divu, -1, 1, 0 );
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TEST_RR_OP(10, divu, -1, 0, 0 );
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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@ -0,0 +1,41 @@
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# See LICENSE for license details.
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#*****************************************************************************
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# rem.S
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#-----------------------------------------------------------------------------
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#
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# Test rem instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Arithmetic tests
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#-------------------------------------------------------------
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TEST_RR_OP( 2, rem, 2, 20, 6 );
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TEST_RR_OP( 3, rem, -2, -20, 6 );
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TEST_RR_OP( 4, rem, 2, 20, -6 );
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TEST_RR_OP( 5, rem, -2, -20, -6 );
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TEST_RR_OP( 6, rem, 0, -1<<63, 1 );
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TEST_RR_OP( 7, rem, 0, -1<<63, -1 );
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TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 );
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TEST_RR_OP( 9, rem, 1, 1, 0 );
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TEST_RR_OP(10, rem, 0, 0, 0 );
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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@ -0,0 +1,41 @@
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# See LICENSE for license details.
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#*****************************************************************************
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# remu.S
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#-----------------------------------------------------------------------------
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#
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# Test remu instruction.
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#
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#include "riscv_test.h"
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#include "test_macros.h"
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RVTEST_RV32U
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RVTEST_CODE_BEGIN
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#-------------------------------------------------------------
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# Arithmetic tests
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#-------------------------------------------------------------
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TEST_RR_OP( 2, remu, 2, 20, 6 );
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TEST_RR_OP( 3, remu, 2, -20, 6 );
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TEST_RR_OP( 4, remu, 20, 20, -6 );
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TEST_RR_OP( 5, remu, -20, -20, -6 );
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TEST_RR_OP( 6, remu, 0, -1<<63, 1 );
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TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 );
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TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 );
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TEST_RR_OP( 9, remu, 1, 1, 0 );
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TEST_RR_OP(10, remu, 0, 0, 0 );
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TEST_PASSFAIL
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RVTEST_CODE_END
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.data
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RVTEST_DATA_BEGIN
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TEST_DATA
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RVTEST_DATA_END
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