Merge branch 'master' into compressed

scripts/cxxdemo/.gitignore

@@ -1,6 +1,7 @@
 firmware.d
 firmware.elf
 firmware.hex
+firmware32.hex
 firmware.o
 syscalls.o
 testbench.exe

scripts/cxxdemo/Makefile

@@ -6,17 +6,18 @@ CCFLAGS = -MD -Os -Wall -std=c++11
 LDFLAGS = -Wl,--gc-sections
 LDLIBS = -lstdc++
 
-test: testbench.exe firmware.hex
+test: testbench.exe firmware32.hex
 	vvp -N testbench.exe
 
 testbench.exe: testbench.v ../../picorv32.v
 	iverilog -o testbench.exe testbench.v ../../picorv32.v
 	chmod -x testbench.exe
 
-firmware.hex: firmware.elf start.elf
+firmware32.hex: firmware.elf start.elf hex8tohex32.py
 	riscv32-unknown-elf-objcopy -O verilog start.elf start.tmp
 	riscv32-unknown-elf-objcopy -O verilog firmware.elf firmware.tmp
 	cat start.tmp firmware.tmp > firmware.hex
+	python3 hex8tohex32.py firmware.hex > firmware32.hex
 	rm -f start.tmp firmware.tmp
 
 firmware.elf: firmware.o syscalls.o
@@ -29,7 +30,7 @@ start.elf: start.S start.ld
 
 clean:
 	rm -f *.o *.d *.tmp start.elf
-	rm -f firmware.elf firmware.hex
+	rm -f firmware.elf firmware.hex firmware32.hex
 	rm -f testbench.exe testbench.vcd
 
 -include *.d

scripts/cxxdemo/hex8tohex32.py

@@ -0,0 +1,34 @@
+#!/usr/bin/env python3
+
+import fileinput
+import itertools
+
+ptr = 0
+data = []
+
+def write_data():
+    if len(data) != 0:
+        print("@%08x" % (ptr >> 2))
+        while len(data) % 4 != 0:
+            data.append(0)
+        for word_bytes in zip(*([iter(data)]*4)):
+            print("".join(["%02x" % b for b in reversed(word_bytes)]))
+
+for line in fileinput.input():
+    if line.startswith("@"):
+        addr = int(line[1:], 16)
+        if addr > ptr+4:
+            write_data()
+            ptr = addr
+            data = []
+            while ptr % 4 != 0:
+                data.append(0)
+                ptr -= 1
+        else:
+            while ptr + len(data) < addr:
+                data.append(0)
+    else:
+        data += [int(tok, 16) for tok in line.split()]
+
+write_data()
+

scripts/cxxdemo/testbench.v

@@ -1,6 +1,7 @@
 `timescale 1 ns / 1 ps
 `undef VERBOSE_MEM
 `undef WRITE_VCD
+`undef MEM8BIT
 
 module testbench;
 	reg clk = 1;
@@ -36,8 +37,13 @@ module testbench;
 	);
 
 	localparam MEM_SIZE = 4*1024*1024;
+`ifdef MEM8BIT
 	reg [7:0] memory [0:MEM_SIZE-1];
 	initial $readmemh("firmware.hex", memory);
+`else
+	reg [31:0] memory [0:MEM_SIZE/4-1];
+	initial $readmemh("firmware32.hex", memory);
+`endif
 
 	always @(posedge clk) begin
 		mem_ready <= 0;
@@ -46,6 +52,7 @@ module testbench;
 			mem_rdata <= 'bx;
 			case (1)
 				mem_addr < MEM_SIZE: begin
+`ifdef MEM8BIT
 					if (|mem_wstrb) begin
 						if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
 						if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
@@ -54,6 +61,16 @@ module testbench;
 					end else begin
 						mem_rdata <= {memory[mem_addr+3], memory[mem_addr+2], memory[mem_addr+1], memory[mem_addr]};
 					end
+`else
+					if (|mem_wstrb) begin
+						if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
+						if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
+						if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
+						if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
+					end else begin
+						mem_rdata <= memory[mem_addr >> 2];
+					end
+`endif
 				end
 				mem_addr == 32'h 1000_0000: begin
 					$write("%c", mem_wdata[7:0]);