testbench_wb.v: fix output stuff
This patch fixes wishbone testbench output issue: 'DNNE' instead of 'DONE', i.e. Cycle counter ......... 546536 Instruction counter .... 69770 CPI: 7.83 DNNE ------------------------------------------------------------ EBREAK instruction at 0x000006C4 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
This commit is contained in:
parent
726a76c1cc
commit
0967a39c1d
|
@ -294,14 +294,13 @@ module wb_ram #(
|
|||
reg [31:0] mem [0:depth/4-1] /* verilator public */;
|
||||
|
||||
always @(posedge wb_clk_i) begin
|
||||
if (adr_r[aw-1:0] == 32'h1000_0000 && wb_stb_i && !wb_ack_o)
|
||||
begin
|
||||
$write("%c", wb_dat_i[7:0]);
|
||||
end else
|
||||
if (adr_r[aw-1:0] == 32'h2000_0000 && wb_stb_i && !wb_ack_o) begin
|
||||
if (wb_dat_i[31:0] == 123456789)
|
||||
tests_passed = 1;
|
||||
end
|
||||
if (ram_we)
|
||||
if (adr_r[aw-1:0] == 32'h1000_0000)
|
||||
$write("%c", wb_dat_i[7:0]);
|
||||
else
|
||||
if (adr_r[aw-1:0] == 32'h2000_0000)
|
||||
if (wb_dat_i[31:0] == 123456789)
|
||||
tests_passed = 1;
|
||||
end
|
||||
|
||||
always @(posedge wb_clk_i) begin
|
||||
|
|
Loading…
Reference in New Issue