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Fix simulation

This commit is contained in:
Miodrag Milanovic 2021-12-27 10:18:30 +01:00
parent 1d9f5b7678
commit 0b87954437
1 changed files with 8 additions and 8 deletions
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16
picosoc/Makefile
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@ -14,13 +14,13 @@ hx8kdemo.json: hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v
yosys -ql hx8kdemo.log -p 'synth_ice40 -top hx8kdemo -json hx8kdemo.json' $^ yosys -ql hx8kdemo.log -p 'synth_ice40 -top hx8kdemo -json hx8kdemo.json' $^
hx8kdemo_tb.vvp: hx8kdemo_tb.v hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v hx8kdemo_tb.vvp: hx8kdemo_tb.v hx8kdemo.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v
iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS
hx8kdemo_syn_tb.vvp: hx8kdemo_tb.v hx8kdemo_syn.v spiflash.v hx8kdemo_syn_tb.vvp: hx8kdemo_tb.v hx8kdemo_syn.v spiflash.v
iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS
hx8kdemo_syn.v: hx8kdemo.blif hx8kdemo_syn.v: hx8kdemo.json
yosys -p 'read_blif -wideports hx8kdemo.blif; write_verilog hx8kdemo_syn.v' yosys -p 'read_json hx8kdemo.json; write_verilog hx8kdemo_syn.v'
hx8kdemo.asc: hx8kdemo.pcf hx8kdemo.json hx8kdemo.asc: hx8kdemo.pcf hx8kdemo.json
nextpnr-ice40 --hx8k --package ct256 --asc hx8kdemo.asc --json hx8kdemo.json --pcf hx8kdemo.pcf nextpnr-ice40 --hx8k --package ct256 --asc hx8kdemo.asc --json hx8kdemo.json --pcf hx8kdemo.pcf
@ -60,10 +60,10 @@ icebreaker.json: icebreaker.v ice40up5k_spram.v spimemio.v simpleuart.v picosoc.
yosys -ql icebreaker.log -p 'synth_ice40 -dsp -top icebreaker -json icebreaker.json' $^ yosys -ql icebreaker.log -p 'synth_ice40 -dsp -top icebreaker -json icebreaker.json' $^
icebreaker_tb.vvp: icebreaker_tb.v icebreaker.v ice40up5k_spram.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v icebreaker_tb.vvp: icebreaker_tb.v icebreaker.v ice40up5k_spram.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v
iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS
icebreaker_syn_tb.vvp: icebreaker_tb.v icebreaker_syn.v spiflash.v icebreaker_syn_tb.vvp: icebreaker_tb.v icebreaker_syn.v spiflash.v
iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` -DNO_ICE40_DEFAULT_ASSIGNMENTS
icebreaker_syn.v: icebreaker.json icebreaker_syn.v: icebreaker.json
yosys -p 'read_json icebreaker.json; write_verilog icebreaker_syn.v' yosys -p 'read_json icebreaker.json; write_verilog icebreaker_syn.v'
@ -96,8 +96,8 @@ icebreaker_fw.bin: icebreaker_fw.elf
# ---- Testbench for SPI Flash Model ---- # ---- Testbench for SPI Flash Model ----
spiflash_tb: spiflash_tb.vvp firmware.hex spiflash_tb: spiflash_tb.vvp icebreaker_fw.hex
vvp -N $< vvp -N $< +firmware=icebreaker_fw.hex
spiflash_tb.vvp: spiflash.v spiflash_tb.v spiflash_tb.vvp: spiflash.v spiflash_tb.v
iverilog -s testbench -o $@ $^ iverilog -s testbench -o $@ $^