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Suppress iverilog warnings re parameters in "make test_synth"

This commit is contained in:
Clifford Wolf 2016-12-15 12:51:31 +01:00
parent ca5702c75f
commit 0bea8428f3
2 changed files with 3 additions and 1 deletions
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2
Makefile
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@ -49,7 +49,7 @@ testbench_sp.vvp: testbench.v picorv32.v
chmod -x testbench_sp.vvp chmod -x testbench_sp.vvp
testbench_synth.vvp: testbench.v synth.v testbench_synth.vvp: testbench.v synth.v
iverilog -o testbench_synth.vvp testbench.v synth.v iverilog -o testbench_synth.vvp -DSYNTH_TEST testbench.v synth.v
chmod -x testbench_synth.vvp chmod -x testbench_synth.vvp
synth.v: picorv32.v scripts/yosys/synth_sim.ys synth.v: picorv32.v scripts/yosys/synth_sim.ys

2
testbench.v
View File

@ -139,6 +139,7 @@ module picorv32_wrapper #(
); );
picorv32_axi #( picorv32_axi #(
`ifndef SYNTH_TEST
`ifdef SP_TEST `ifdef SP_TEST
.ENABLE_REGS_DUALPORT(0), .ENABLE_REGS_DUALPORT(0),
`endif `endif
@ -149,6 +150,7 @@ module picorv32_wrapper #(
.ENABLE_DIV(1), .ENABLE_DIV(1),
.ENABLE_IRQ(1), .ENABLE_IRQ(1),
.ENABLE_TRACE(1) .ENABLE_TRACE(1)
`endif
) uut ( ) uut (
.clk (clk ), .clk (clk ),
.resetn (resetn ), .resetn (resetn ),