Progress with smt2-based bmc scripts
This commit is contained in:
Clifford Wolf
parent
93d78f38d8
commit
12e64c7968
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@ -1,3 +1,6 @@
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debug.smt2
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mem_equiv_a.smt2
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mem_equiv_b.smt2
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mem_equiv_tb
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mem_equiv_tb.v
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mem_equiv_tb.vcd
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@ -1,11 +1,15 @@
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#!/usr/bin/python3
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import sys, getopt
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import os, sys, getopt
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import subprocess
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steps=15
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steps = 20
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debug_print = False
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debug_file = None # open("debug.smt2", "w")
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debug_file = open("debug.smt2", "w")
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# Yices Bindings
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#####################################
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yices = subprocess.Popen(['yices-smt2', '--incremental'], stdin=subprocess.PIPE,
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stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
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@ -76,15 +80,44 @@ def yices_parse(stmt):
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return expr, cursor
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return worker(stmt)[0]
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def yices_get(mod_name, net_name, state_name):
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yices_write("(get-value ((|%s_n %s| %s)))" % (mod_name, net_name, state_name))
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def yices_bv2hex(v):
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h = ""
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while len(v) > 2:
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d = 0
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if len(v) > 0 and v[-1] == "1": d += 1
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if len(v) > 1 and v[-2] == "1": d += 2
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if len(v) > 2 and v[-3] == "1": d += 4
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if len(v) > 3 and v[-4] == "1": d += 8
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h = hex(d)[2:] + h
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if len(v) < 4: break
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v = v[:-4]
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return h
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def yices_bv2bin(v):
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return v[2:]
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def yices_get(expr):
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yices_write("(get-value (%s))" % (expr))
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return yices_parse(yices_read())[0][1]
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def yices_get_bool(mod_name, net_name, state_name):
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v = yices_get(mod_name, net_name, state_name)
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def yices_get_net(mod_name, net_name, state_name):
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return yices_get("(|%s_n %s| %s)" % (mod_name, net_name, state_name))
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def yices_get_net_bool(mod_name, net_name, state_name):
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v = yices_get_net(mod_name, net_name, state_name)
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assert v in ["true", "false"]
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return 1 if v == "true" else 0
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def yices_get_net_hex(mod_name, net_name, state_name):
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return yices_bv2hex(yices_get_net(mod_name, net_name, state_name))
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def yices_get_net_bin(mod_name, net_name, state_name):
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return yices_bv2bin(yices_get_net(mod_name, net_name, state_name))
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# Main Program
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#####################################
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yices_write("(set-logic QF_AUFBV)")
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with open("mem_equiv_a.smt2", "r") as f:
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@ -116,34 +149,55 @@ yices_write("(assert (not (|main_a_n mem_valid| a%d)))" % (steps-1))
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yices_write("(assert (not (|main_b_n mem_valid| b%d)))" % (steps-1))
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yices_write("(assert (|main_a_n trap| a%d))" % (steps-1))
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yices_write("(assert (|main_b_n trap| b%d))" % (steps-1))
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yices_write("(assert (|main_a_n trap| a%d))" % (steps-2))
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yices_write("(assert (|main_b_n trap| b%d))" % (steps-2))
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# look for differences in memory or register file
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yices_write(("(assert (or (distinct (|main_a_m cpu.cpuregs| a%d) (|main_b_m cpu.cpuregs| b%d)) " +
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"(distinct (|main_a_m memory| a%d) (|main_b_m memory| b%d))))") % (steps-1, steps-1, steps-1, steps-1))
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def make_cpu_regs(step):
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for i in range(1, 32):
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yices_write("(define-fun a%d_r%d () (_ BitVec 32) (select (|main_a_m cpu.cpuregs| a%d) #b%s))" % (step, i, step, bin(32+i)[3:]))
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yices_write("(define-fun b%d_r%d () (_ BitVec 32) (select (|main_b_m cpu.cpuregs| b%d) #b%s))" % (step, i, step, bin(32+i)[3:]))
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make_cpu_regs(0)
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make_cpu_regs(steps-1)
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print("checking...")
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yices_write("(check-sat)")
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def print_status(mod, step):
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resetn = yices_get_bool("main_" + mod, "resetn", "%s%d" % (mod, step))
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memvld = yices_get_bool("main_" + mod, "mem_valid", "%s%d" % (mod, step))
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domem = yices_get_bool("main_" + mod, "domem", "%s%d" % (mod, step))
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memrdy = yices_get_bool("main_" + mod, "mem_ready", "%s%d" % (mod, step))
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trap = yices_get_bool("main_" + mod, "trap", "%s%d" % (mod, step))
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print("%s[%d]: resetn=%s, memvld=%s, domem=%s, memrdy=%s, trap=%s" % (mod, step, resetn, memvld, domem, memrdy, trap))
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resetn = yices_get_net_bool("main_" + mod, "resetn", "%s%d" % (mod, step))
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memvld = yices_get_net_bool("main_" + mod, "mem_valid", "%s%d" % (mod, step))
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domem = yices_get_net_bool("main_" + mod, "domem", "%s%d" % (mod, step))
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memrdy = yices_get_net_bool("main_" + mod, "mem_ready", "%s%d" % (mod, step))
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trap = yices_get_net_bool("main_" + mod, "trap", "%s%d" % (mod, step))
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print("status %5s: resetn=%s, memvld=%s, domem=%s, memrdy=%s, trap=%s" % ("%s[%d]" % (mod, step), resetn, memvld, domem, memrdy, trap))
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def print_mem_xfer(mod, step):
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yices_write("(get-value ((and (|main_%s_n mem_valid| %s%d) (|main_%s_n mem_ready| %s%d))))" % (mod, mod, step, mod, mod, step))
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if yices_parse(yices_read())[0][1] == 'true':
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mem_addr = yices_get("main_" + mod, "mem_addr", "%s%d" % (mod, step))
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mem_wdata = yices_get("main_" + mod, "mem_wdata", "%s%d" % (mod, step))
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mem_wstrb = yices_get("main_" + mod, "mem_wstrb", "%s%d" % (mod, step))
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mem_rdata = yices_get("main_" + mod, "mem_rdata", "%s%d" % (mod, step))
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print("%s[%d]: addr=%s, wdata=%s, wstrb=%s, rdata=%s" % (mod, step, mem_addr, mem_wdata, mem_wstrb, mem_rdata))
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if yices_get("(and (|main_%s_n mem_valid| %s%d) (|main_%s_n mem_ready| %s%d))" % (mod, mod, step, mod, mod, step)) == 'true':
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mem_addr = yices_get_net_hex("main_" + mod, "mem_addr", "%s%d" % (mod, step))
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mem_wdata = yices_get_net_hex("main_" + mod, "mem_wdata", "%s%d" % (mod, step))
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mem_wstrb = yices_get_net_bin("main_" + mod, "mem_wstrb", "%s%d" % (mod, step))
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mem_rdata = yices_get_net_hex("main_" + mod, "mem_rdata", "%s%d" % (mod, step))
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print("mem %5s: addr=%s, wdata=%s, wstrb=%s, rdata=%s" % ("%s[%d]" % (mod, step), mem_addr, mem_wdata, mem_wstrb, mem_rdata))
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def print_cpu_regs(step):
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for i in range(1, 32):
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ra = yices_bv2hex(yices_get("a%d_r%d" % (step, i)))
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rb = yices_bv2hex(yices_get("b%d_r%d" % (step, i)))
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print("%3s[%d]: A=%s B=%s%s" % ("x%d" % i, step, ra, rb, " !" if ra != rb else ""))
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if yices_read() == "sat":
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print("yices returned sat -> model check failed!")
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print()
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print_cpu_regs(0)
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print()
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print_cpu_regs(steps-1)
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print()
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for i in range(steps):
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print_status("a", i)
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@ -160,6 +214,108 @@ if yices_read() == "sat":
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for i in range(1, steps):
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print_mem_xfer("b", i)
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with open("mem_equiv_tb.v", "w") as f:
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print()
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print("writing verilog test bench...")
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memory_words = 1
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memory_datas = { "a": dict(), "b": dict() }
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for i in range(steps-1, 0, -1):
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for mod in ["a", "b"]:
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if yices_get("(and (|main_%s_n mem_valid| %s%d) (|main_%s_n mem_ready| %s%d))" % (mod, mod, i, mod, mod, i)) == 'true':
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mem_addr = yices_get_net_hex("main_" + mod, "mem_addr", "%s%d" % (mod, i))
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mem_rdata = yices_get_net_hex("main_" + mod, "mem_rdata", "%s%d" % (mod, i))
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memory_datas[mod][mem_addr] = mem_rdata
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memory_words = max(int(mem_addr, 16)+1, memory_words)
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memory_data = dict()
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for k, v in memory_datas["a"].items(): memory_data[k] = v
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for k, v in memory_datas["b"].items(): memory_data[k] = v
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print("`timescale 1 ns / 1 ps", file=f)
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print("", file=f)
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print("module testbench;", file=f)
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print(" reg clk = 1, resetn, domem_a, domem_b;", file=f)
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print(" always #5 clk = ~clk;", file=f)
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print("", file=f)
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print(" main #(", file=f)
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print(" .MEMORY_WORDS(%d)," % memory_words, file=f)
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print(" .ENABLE_REGS_DUALPORT(0),", file=f)
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print(" .TWO_STAGE_SHIFT(0),", file=f)
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print(" .TWO_CYCLE_COMPARE(0),", file=f)
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print(" .TWO_CYCLE_ALU(0)", file=f)
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print(" ) main_a (", file=f)
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print(" .clk(clk),", file=f)
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print(" .resetn(resetn),", file=f)
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print(" .domem(domem_a)", file=f)
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print(" );", file=f)
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print("", file=f)
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print(" main #(", file=f)
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print(" .MEMORY_WORDS(%d)," % memory_words, file=f)
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print(" .ENABLE_REGS_DUALPORT(1),", file=f)
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print(" .TWO_STAGE_SHIFT(1),", file=f)
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print(" .TWO_CYCLE_COMPARE(1),", file=f)
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print(" .TWO_CYCLE_ALU(1)", file=f)
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print(" ) main_b (", file=f)
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print(" .clk(clk),", file=f)
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print(" .resetn(resetn),", file=f)
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print(" .domem(domem_b)", file=f)
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print(" );", file=f)
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print("", file=f)
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print(" task check_reg;", file=f)
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print(" input [4:0] n;", file=f)
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print(" begin", file=f)
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print(" if (main_a.cpu.cpuregs[n] != main_b.cpu.cpuregs[n])", file=f)
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print(" $display(\"Divergent values for reg %1d: A=%08x B=%08x\", n, main_a.cpu.cpuregs[n], main_b.cpu.cpuregs[n]);", file=f)
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print(" end", file=f)
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print(" endtask", file=f)
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print("", file=f)
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print(" task check_mem;", file=f)
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print(" input [31:0] n;", file=f)
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print(" begin", file=f)
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print(" if (main_a.memory[n] != main_b.memory[n])", file=f)
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print(" $display(\"Divergent values for memory addr %08x: A=%08x B=%08x\", n, main_a.cpu.cpuregs[n], main_b.cpu.cpuregs[n]);", file=f)
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print(" end", file=f)
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print(" endtask", file=f)
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print("", file=f)
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print(" initial begin", file=f)
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print(" $dumpfile(\"mem_equiv_tb.vcd\");", file=f)
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print(" $dumpvars(0, testbench);", file=f)
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print("", file=f)
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for i in range(1, 32):
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ra = yices_bv2hex(yices_get("a%d_r%d" % (0, i)))
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rb = yices_bv2hex(yices_get("b%d_r%d" % (0, i)))
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print(" main_a.cpu.cpuregs[%2d] = 'h %s; main_b.cpu.cpuregs[%2d] = 'h %s;" % (i, ra, i, rb), file=f)
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print("", file=f)
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for addr, data in memory_data.items():
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print(" main_a.memory['h %s] = 'h %s;" % (addr, data), file=f)
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print(" main_b.memory['h %s] = 'h %s;" % (addr, data), file=f)
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print("", file=f)
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for i in range(steps):
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print(" resetn = %d;" % yices_get_net_bool("main_a", "resetn", "a%d" % i), file=f)
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print(" domem_a = %d;" % yices_get_net_bool("main_a", "domem", "a%d" % i), file=f)
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print(" domem_b = %d;" % yices_get_net_bool("main_b", "domem", "b%d" % i), file=f)
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print(" @(posedge clk);", file=f)
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print("", file=f)
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for i in range(1, 32):
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print(" check_reg(%d);" % i, file=f)
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for addr, data in memory_data.items():
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print(" check_mem('h %s);" % addr, file=f)
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print("", file=f)
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print(" $finish;", file=f)
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print(" end", file=f)
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print("endmodule", file=f)
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print("running verilog test bench...")
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os.system("iverilog -o mem_equiv_tb -s testbench mem_equiv_tb.v mem_equiv.v ../../picorv32.v && ./mem_equiv_tb")
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else:
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print("yices returned unsat -> model check passed.")
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yices_write("(exit)")
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yices.wait()
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@ -1,4 +1,7 @@
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`timescale 1 ns / 1 ps
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module main (input clk, resetn, domem, output trap);
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parameter integer MEMORY_WORDS = 2**30;
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parameter [0:0] ENABLE_REGS_DUALPORT = 1;
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parameter [0:0] TWO_STAGE_SHIFT = 1;
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parameter [0:0] TWO_CYCLE_COMPARE = 0;
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@ -28,7 +31,7 @@ module main (input clk, resetn, domem, output trap);
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.mem_rdata(mem_rdata)
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);
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reg [31:0] memory [0:2**30-1];
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reg [31:0] memory [0:MEMORY_WORDS-1];
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assign mem_ready = domem && resetn && mem_valid;
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assign mem_rdata = memory[mem_addr >> 2];
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