remove WITH_PCPI.
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18
picorv32.v
18
picorv32.v
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@ -103,9 +103,6 @@ module picorv32 #(
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localparam integer irqregs_offset = 32;
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localparam integer irqregs_offset = 32;
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localparam integer regfile_size = 32 + 4;
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localparam integer regfile_size = 32 + 4;
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localparam integer regindex_bits = 5 + 1;
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localparam integer regindex_bits = 5 + 1;
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localparam WITH_PCPI = 1; // AAAA
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localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
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localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
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localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0};
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localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0};
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localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0};
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localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0};
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@ -617,7 +614,7 @@ module picorv32 #(
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end
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end
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if (decoder_trigger && !decoder_pseudo_trigger) begin
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if (decoder_trigger && !decoder_pseudo_trigger) begin
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pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx;
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pcpi_insn <= mem_rdata_q;
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instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
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instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
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instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
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instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
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@ -940,14 +937,12 @@ module picorv32 #(
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dbg_rs2val_valid <= 0;
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dbg_rs2val_valid <= 0;
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end
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end
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if (WITH_PCPI) begin
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if (resetn && pcpi_valid && !pcpi_int_wait) begin
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if (resetn && pcpi_valid && !pcpi_int_wait) begin
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if (pcpi_timeout_counter)
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if (pcpi_timeout_counter)
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pcpi_timeout_counter <= pcpi_timeout_counter - 1;
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pcpi_timeout_counter <= pcpi_timeout_counter - 1;
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end else
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end else
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pcpi_timeout_counter <= ~0;
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pcpi_timeout_counter <= ~0;
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pcpi_timeout <= !pcpi_timeout_counter;
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pcpi_timeout <= !pcpi_timeout_counter;
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end
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count_cycle <= resetn ? count_cycle + 1 : 0;
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count_cycle <= resetn ? count_cycle + 1 : 0;
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next_irq_pending = irq_pending & LATCHED_IRQ;
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next_irq_pending = irq_pending & LATCHED_IRQ;
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@ -1088,7 +1083,6 @@ module picorv32 #(
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(* parallel_case *)
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(* parallel_case *)
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case (1'b1)
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case (1'b1)
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instr_trap: begin
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instr_trap: begin
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if (WITH_PCPI) begin
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
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`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
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reg_op1 <= cpuregs_rs1;
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reg_op1 <= cpuregs_rs1;
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dbg_rs1val <= cpuregs_rs1;
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dbg_rs1val <= cpuregs_rs1;
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@ -1115,14 +1109,6 @@ module picorv32 #(
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end else
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end else
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cpu_state <= cpu_state_trap;
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cpu_state <= cpu_state_trap;
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end
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end
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end else begin
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`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
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if (!irq_mask[irq_ebreak] && !irq_active) begin
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next_irq_pending[irq_ebreak] = 1;
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cpu_state <= cpu_state_fetch;
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end else
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cpu_state <= cpu_state_trap;
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end
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end
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end
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is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
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is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
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(* parallel_case, full_case *)
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(* parallel_case, full_case *)
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@ -1263,7 +1249,7 @@ module picorv32 #(
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(* parallel_case *)
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(* parallel_case *)
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case (1'b1)
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case (1'b1)
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WITH_PCPI && instr_trap: begin
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instr_trap: begin
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pcpi_valid <= 1;
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pcpi_valid <= 1;
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if (pcpi_int_ready) begin
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if (pcpi_int_ready) begin
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mem_do_rinst <= 1;
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mem_do_rinst <= 1;
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