remove WITH_PCPI.
This commit is contained in:
parent
92b7265264
commit
1436980611
68
picorv32.v
68
picorv32.v
|
@ -103,9 +103,6 @@ module picorv32 #(
|
||||||
localparam integer irqregs_offset = 32;
|
localparam integer irqregs_offset = 32;
|
||||||
localparam integer regfile_size = 32 + 4;
|
localparam integer regfile_size = 32 + 4;
|
||||||
localparam integer regindex_bits = 5 + 1;
|
localparam integer regindex_bits = 5 + 1;
|
||||||
|
|
||||||
localparam WITH_PCPI = 1; // AAAA
|
|
||||||
|
|
||||||
localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
|
localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
|
||||||
localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0};
|
localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0};
|
||||||
localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0};
|
localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0};
|
||||||
|
@ -617,7 +614,7 @@ module picorv32 #(
|
||||||
end
|
end
|
||||||
|
|
||||||
if (decoder_trigger && !decoder_pseudo_trigger) begin
|
if (decoder_trigger && !decoder_pseudo_trigger) begin
|
||||||
pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx;
|
pcpi_insn <= mem_rdata_q;
|
||||||
|
|
||||||
instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
|
instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
|
||||||
instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
|
instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
|
||||||
|
@ -940,14 +937,12 @@ module picorv32 #(
|
||||||
dbg_rs2val_valid <= 0;
|
dbg_rs2val_valid <= 0;
|
||||||
end
|
end
|
||||||
|
|
||||||
if (WITH_PCPI) begin
|
if (resetn && pcpi_valid && !pcpi_int_wait) begin
|
||||||
if (resetn && pcpi_valid && !pcpi_int_wait) begin
|
if (pcpi_timeout_counter)
|
||||||
if (pcpi_timeout_counter)
|
pcpi_timeout_counter <= pcpi_timeout_counter - 1;
|
||||||
pcpi_timeout_counter <= pcpi_timeout_counter - 1;
|
end else
|
||||||
end else
|
pcpi_timeout_counter <= ~0;
|
||||||
pcpi_timeout_counter <= ~0;
|
pcpi_timeout <= !pcpi_timeout_counter;
|
||||||
pcpi_timeout <= !pcpi_timeout_counter;
|
|
||||||
end
|
|
||||||
count_cycle <= resetn ? count_cycle + 1 : 0;
|
count_cycle <= resetn ? count_cycle + 1 : 0;
|
||||||
next_irq_pending = irq_pending & LATCHED_IRQ;
|
next_irq_pending = irq_pending & LATCHED_IRQ;
|
||||||
|
|
||||||
|
@ -1088,34 +1083,25 @@ module picorv32 #(
|
||||||
(* parallel_case *)
|
(* parallel_case *)
|
||||||
case (1'b1)
|
case (1'b1)
|
||||||
instr_trap: begin
|
instr_trap: begin
|
||||||
if (WITH_PCPI) begin
|
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
|
||||||
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
|
reg_op1 <= cpuregs_rs1;
|
||||||
reg_op1 <= cpuregs_rs1;
|
dbg_rs1val <= cpuregs_rs1;
|
||||||
dbg_rs1val <= cpuregs_rs1;
|
dbg_rs1val_valid <= 1;
|
||||||
dbg_rs1val_valid <= 1;
|
pcpi_valid <= 1;
|
||||||
pcpi_valid <= 1;
|
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
|
||||||
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
|
reg_sh <= cpuregs_rs2;
|
||||||
reg_sh <= cpuregs_rs2;
|
reg_op2 <= cpuregs_rs2;
|
||||||
reg_op2 <= cpuregs_rs2;
|
dbg_rs2val <= cpuregs_rs2;
|
||||||
dbg_rs2val <= cpuregs_rs2;
|
dbg_rs2val_valid <= 1;
|
||||||
dbg_rs2val_valid <= 1;
|
if (pcpi_int_ready) begin
|
||||||
if (pcpi_int_ready) begin
|
mem_do_rinst <= 1;
|
||||||
mem_do_rinst <= 1;
|
pcpi_valid <= 0;
|
||||||
pcpi_valid <= 0;
|
reg_out <= pcpi_int_rd;
|
||||||
reg_out <= pcpi_int_rd;
|
latched_store <= pcpi_int_wr;
|
||||||
latched_store <= pcpi_int_wr;
|
cpu_state <= cpu_state_fetch;
|
||||||
cpu_state <= cpu_state_fetch;
|
end else
|
||||||
end else
|
if (pcpi_timeout || instr_ecall_ebreak) begin
|
||||||
if (pcpi_timeout || instr_ecall_ebreak) begin
|
pcpi_valid <= 0;
|
||||||
pcpi_valid <= 0;
|
|
||||||
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
|
|
||||||
if (!irq_mask[irq_ebreak] && !irq_active) begin
|
|
||||||
next_irq_pending[irq_ebreak] = 1;
|
|
||||||
cpu_state <= cpu_state_fetch;
|
|
||||||
end else
|
|
||||||
cpu_state <= cpu_state_trap;
|
|
||||||
end
|
|
||||||
end else begin
|
|
||||||
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
|
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
|
||||||
if (!irq_mask[irq_ebreak] && !irq_active) begin
|
if (!irq_mask[irq_ebreak] && !irq_active) begin
|
||||||
next_irq_pending[irq_ebreak] = 1;
|
next_irq_pending[irq_ebreak] = 1;
|
||||||
|
@ -1263,7 +1249,7 @@ module picorv32 #(
|
||||||
|
|
||||||
(* parallel_case *)
|
(* parallel_case *)
|
||||||
case (1'b1)
|
case (1'b1)
|
||||||
WITH_PCPI && instr_trap: begin
|
instr_trap: begin
|
||||||
pcpi_valid <= 1;
|
pcpi_valid <= 1;
|
||||||
if (pcpi_int_ready) begin
|
if (pcpi_int_ready) begin
|
||||||
mem_do_rinst <= 1;
|
mem_do_rinst <= 1;
|
||||||
|
|
Loading…
Reference in New Issue