Changed chip package in vivado examples
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read_verilog ../../picorv32.v
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read_verilog ../../picorv32.v
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read_xdc synth_area.xdc
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read_xdc synth_area.xdc
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synth_design -part xc7a15t-csg324 -top picorv32_axi
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synth_design -part xc7a15t-fgg484 -top picorv32_axi
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opt_design
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opt_design
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place_design
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place_design
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route_design
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route_design
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@ -2,7 +2,7 @@
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read_verilog ../../picorv32.v
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read_verilog ../../picorv32.v
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read_xdc synth_speed.xdc
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read_xdc synth_speed.xdc
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synth_design -part xc7a15t-csg324 -top picorv32_axi
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synth_design -part xc7a15t-fgg484 -top picorv32_axi
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opt_design
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opt_design
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place_design
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place_design
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route_design
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route_design
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