Add PicoSoC IceBreaker demo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
b634224ccb
commit
1afe3af452
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@ -11,5 +11,13 @@
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/hx8kdemo_syn.v
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/hx8kdemo_syn_tb.vvp
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/hx8kdemo_tb.vvp
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/icebreaker.asc
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/icebreaker.bin
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/icebreaker.json
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/icebreaker.log
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/icebreaker.rpt
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/icebreaker_syn.v
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/icebreaker_syn_tb.vvp
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/icebreaker_tb.vvp
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/testbench.vcd
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/cmos.log
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@ -33,10 +33,44 @@ hx8kprog: hx8kdemo.bin firmware.bin
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hx8kprog_fw: firmware.bin
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iceprog -o 1M firmware.bin
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# ---- iCE40 IceBreaker Board ----
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icebsim: icebreaker_tb.vvp firmware.hex
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vvp -N $<
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icebsynsim: icebreaker_syn_tb.vvp firmware.hex
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vvp -N $<
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icebreaker.json: icebreaker.v spimemio.v simpleuart.v picosoc.v ../picorv32.v
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yosys -ql icebreaker.log -p 'synth_ice40 -top icebreaker -json icebreaker.json' $^
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icebreaker_tb.vvp: icebreaker_tb.v icebreaker.v spimemio.v simpleuart.v picosoc.v ../picorv32.v spiflash.v
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iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
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icebreaker_syn_tb.vvp: icebreaker_tb.v icebreaker_syn.v spiflash.v
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iverilog -s testbench -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
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icebreaker_syn.v: icebreaker.json
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yosys -p 'read_json icebreaker.json; write_verilog icebreaker_syn.v'
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icebreaker.asc: icebreaker.pcf icebreaker.json
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nextpnr-ice40 --freq 13 --up5k --asc icebreaker.asc --pcf icebreaker.pcf --json icebreaker.json
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icebreaker.bin: icebreaker.asc
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icetime -d up5k -c 12 -mtr icebreaker.rpt icebreaker.asc
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icepack icebreaker.asc icebreaker.bin
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icebprog: icebreaker.bin firmware.bin
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iceprog icebreaker.bin
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iceprog -o 1M firmware.bin
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icebprog_fw: firmware.bin
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iceprog -o 1M firmware.bin
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# ---- Example Firmware ----
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firmware.elf: sections.lds start.s firmware.c
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riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o firmware.elf start.s firmware.c
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riscv32-unknown-elf-gcc -march=rv32ic -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o firmware.elf start.s firmware.c
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firmware.hex: firmware.elf
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riscv32-unknown-elf-objcopy -O verilog firmware.elf firmware.hex
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@ -64,6 +98,9 @@ clean:
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rm -f firmware.elf firmware.hex firmware.bin cmos.log
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rm -f hx8kdemo.blif hx8kdemo.log hx8kdemo.asc hx8kdemo.rpt hx8kdemo.bin
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rm -f hx8kdemo_syn.v hx8kdemo_syn_tb.vvp hx8kdemo_tb.vvp
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rm -f icebreaker.json icebreaker.log icebreaker.asc icebreaker.rpt icebreaker.bin
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rm -f icebreaker_syn.v icebreaker_syn_tb.vvp icebreaker_tb.vvp
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.PHONY: spiflash_tb hx8kprog hx8kprog_fw hx8ksim hx8ksynsim clean
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.PHONY: spiflash_tb clean
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.PHONY: hx8kprog hx8kprog_fw hx8ksim hx8ksynsim
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.PHONY: icebprog icebprog_fw icebsim icebsynsim
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@ -32,7 +32,7 @@ void set_flash_qspi_flag()
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{
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uint8_t buffer[8];
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#if 0
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#if 1
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uint32_t addr_cr1v = 0x800002;
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// Read Any Register (RDAR 65h)
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@ -0,0 +1,25 @@
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# 12 MHz clock
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set_io clk 35
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# RS232
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set_io ser_rx 6
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set_io ser_tx 9
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# SPI Flash
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set_io flash_clk 15
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set_io flash_csb 16
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set_io flash_io0 14
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set_io flash_io1 17
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set_io flash_io2 12
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set_io flash_io3 13
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# LEDs (PMOD 2)
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set_io led1 27
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set_io led2 25
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set_io led3 21
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set_io led4 23
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set_io led5 26
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# Onboard LEDs
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set_io ledr_n 11
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set_io ledg_n 37
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@ -0,0 +1,140 @@
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/*
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* PicoSoC - A simple example SoC using PicoRV32
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module icebreaker (
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input clk,
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output ser_tx,
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input ser_rx,
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output led1,
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output led2,
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output led3,
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output led4,
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output led5,
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output ledr_n,
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output ledg_n,
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output flash_csb,
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output flash_clk,
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inout flash_io0,
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inout flash_io1,
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inout flash_io2,
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inout flash_io3
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);
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reg [5:0] reset_cnt = 0;
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wire resetn = &reset_cnt;
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always @(posedge clk) begin
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reset_cnt <= reset_cnt + !resetn;
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end
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wire [7:0] leds;
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assign led1 = leds[1];
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assign led2 = leds[2];
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assign led3 = leds[3];
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assign led4 = leds[4];
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assign led5 = leds[5];
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assign ledr_n = !leds[6];
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assign ledg_n = !leds[7];
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wire flash_io0_oe, flash_io0_do, flash_io0_di;
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wire flash_io1_oe, flash_io1_do, flash_io1_di;
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wire flash_io2_oe, flash_io2_do, flash_io2_di;
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wire flash_io3_oe, flash_io3_do, flash_io3_di;
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SB_IO #(
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.PIN_TYPE(6'b 1010_01),
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.PULLUP(1'b 0)
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) flash_io_buf [3:0] (
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.PACKAGE_PIN({flash_io3, flash_io2, flash_io1, flash_io0}),
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.OUTPUT_ENABLE({flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe}),
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.D_OUT_0({flash_io3_do, flash_io2_do, flash_io1_do, flash_io0_do}),
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.D_IN_0({flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di})
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);
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wire iomem_valid;
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reg iomem_ready;
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wire [3:0] iomem_wstrb;
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wire [31:0] iomem_addr;
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wire [31:0] iomem_wdata;
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reg [31:0] iomem_rdata;
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reg [31:0] gpio;
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assign leds = gpio;
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always @(posedge clk) begin
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if (!resetn) begin
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gpio <= 0;
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end else begin
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iomem_ready <= 0;
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if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
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iomem_ready <= 1;
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iomem_rdata <= gpio;
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if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
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if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
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if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
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if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
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end
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end
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end
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picosoc #(
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.BARREL_SHIFTER(0),
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.ENABLE_MULDIV(0)
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) soc (
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.clk (clk ),
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.resetn (resetn ),
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.ser_tx (ser_tx ),
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.ser_rx (ser_rx ),
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.flash_csb (flash_csb ),
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.flash_clk (flash_clk ),
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.flash_io0_oe (flash_io0_oe),
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.flash_io1_oe (flash_io1_oe),
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.flash_io2_oe (flash_io2_oe),
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.flash_io3_oe (flash_io3_oe),
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.flash_io0_do (flash_io0_do),
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.flash_io1_do (flash_io1_do),
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.flash_io2_do (flash_io2_do),
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.flash_io3_do (flash_io3_do),
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.flash_io0_di (flash_io0_di),
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.flash_io1_di (flash_io1_di),
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.flash_io2_di (flash_io2_di),
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.flash_io3_di (flash_io3_di),
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.irq_5 (1'b0 ),
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.irq_6 (1'b0 ),
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.irq_7 (1'b0 ),
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.iomem_valid (iomem_valid ),
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.iomem_ready (iomem_ready ),
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.iomem_wstrb (iomem_wstrb ),
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.iomem_addr (iomem_addr ),
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.iomem_wdata (iomem_wdata ),
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.iomem_rdata (iomem_rdata )
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);
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endmodule
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@ -0,0 +1,117 @@
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/*
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* PicoSoC - A simple example SoC using PicoRV32
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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`timescale 1 ns / 1 ps
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module testbench;
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reg clk;
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always #5 clk = (clk === 1'b0);
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localparam ser_half_period = 53;
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event ser_sample;
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initial begin
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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repeat (6) begin
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repeat (50000) @(posedge clk);
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$display("+50000 cycles");
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end
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$finish;
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end
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integer cycle_cnt = 0;
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always @(posedge clk) begin
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cycle_cnt <= cycle_cnt + 1;
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end
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wire led1, led2, led3, led4, led5;
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wire ledr_n, ledg_n;
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wire [6:0] leds = {!ledg_n, !ledr_n, led5, led4, led3, led2, led1};
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wire ser_rx;
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wire ser_tx;
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wire flash_csb;
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wire flash_clk;
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wire flash_io0;
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wire flash_io1;
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wire flash_io2;
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wire flash_io3;
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always @(leds) begin
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#1 $display("%b", leds);
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end
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icebreaker uut (
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.clk (clk ),
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.led1 (led1 ),
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.led2 (led2 ),
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.led3 (led3 ),
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.led4 (led4 ),
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.led5 (led5 ),
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.ledr_n (ledr_n ),
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.ledg_n (ledg_n ),
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.ser_rx (ser_rx ),
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.ser_tx (ser_tx ),
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.flash_csb(flash_csb),
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.flash_clk(flash_clk),
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.flash_io0(flash_io0),
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.flash_io1(flash_io1),
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.flash_io2(flash_io2),
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.flash_io3(flash_io3)
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);
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spiflash spiflash (
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.csb(flash_csb),
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.clk(flash_clk),
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.io0(flash_io0),
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.io1(flash_io1),
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.io2(flash_io2),
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.io3(flash_io3)
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);
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reg [7:0] buffer;
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always begin
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@(negedge ser_tx);
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repeat (ser_half_period) @(posedge clk);
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-> ser_sample; // start bit
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repeat (8) begin
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repeat (ser_half_period) @(posedge clk);
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repeat (ser_half_period) @(posedge clk);
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buffer = {ser_tx, buffer[7:1]};
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-> ser_sample; // data bit
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end
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repeat (ser_half_period) @(posedge clk);
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repeat (ser_half_period) @(posedge clk);
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-> ser_sample; // stop bit
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if (buffer < 32 || buffer >= 127)
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$display("Serial data: %d", buffer);
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else
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$display("Serial data: '%c'", buffer);
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end
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endmodule
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@ -61,7 +61,12 @@ module picosoc (
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input flash_io2_di,
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input flash_io3_di
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);
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parameter [0:0] BARREL_SHIFTER = 1;
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parameter [0:0] ENABLE_MULDIV = 1;
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parameter [0:0] ENABLE_COMPRESSED = 1;
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parameter [0:0] ENABLE_COUNTERS = 1;
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parameter [0:0] ENABLE_IRQ_QREGS = 0;
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parameter integer MEM_WORDS = 256;
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parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
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parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash
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@ -120,10 +125,11 @@ module picosoc (
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.STACKADDR(STACKADDR),
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.PROGADDR_RESET(PROGADDR_RESET),
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.PROGADDR_IRQ(PROGADDR_IRQ),
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.BARREL_SHIFTER(1),
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.COMPRESSED_ISA(1),
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.ENABLE_MUL(1),
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.ENABLE_DIV(1),
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.BARREL_SHIFTER(BARREL_SHIFTER),
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.COMPRESSED_ISA(ENABLE_COMPRESSED),
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.ENABLE_COUNTERS(ENABLE_COUNTERS),
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.ENABLE_MUL(ENABLE_MULDIV),
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.ENABLE_DIV(ENABLE_MULDIV),
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.ENABLE_IRQ(1),
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.ENABLE_IRQ_QREGS(ENABLE_IRQ_QREGS)
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) cpu (
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