Added scripts/csmith/ verilator support

scripts/csmith/.gitignore

@@ -1,3 +1,4 @@
+obj_dir
 riscv-fesvr
 riscv-isa-sim
 output_ref.txt

scripts/csmith/Makefile

@@ -2,16 +2,36 @@ RISCV_TOOLS_DIR = /opt/riscv32imc
 RISCV_TOOLS_PREFIX = $(RISCV_TOOLS_DIR)/bin/riscv32-unknown-elf-
 CSMITH_INCDIR = $(shell ls -d /usr/local/include/csmith-* | head -n1)
 CC = $(RISCV_TOOLS_PREFIX)gcc
+SHELL = /bin/bash
 
-run: test_ref test.hex testbench.vvp
+help:
+	@echo "Usage: make { loop | verilator | iverilog | spike }"
+
+loop:
+	+set -e; x() { echo "$$*" >&2; "$$@"; }; while true; do \
+		echo; echo; rm -f output_ref.txt output_sim.txt; \
+		echo "-----------------------------------------"; \
+		x rm -f test.hex test.elf test.c test_ref test.ld; \
+		x $(MAKE) test_ref test.hex obj_dir/Vtestbench; \
+		x timeout 1 ./test_ref > >( tee output_ref.txt; ) || { echo TIMEOUT; continue; }; \
+		x obj_dir/Vtestbench > >( tee /dev/stderr | grep -v '$$finish' > output_sim.txt; ); \
+		sleep 1; x diff -u output_ref.txt output_sim.txt; echo "OK."; \
+	done
+
+verilator: test_ref test.hex obj_dir/Vtestbench
+	./test_ref | tee output_ref.txt
+	obj_dir/Vtestbench | grep -v '$$finish' | tee output_sim.txt
+	diff -u output_ref.txt output_sim.txt
+
+iverilog: test_ref test.hex testbench.vvp
 	./test_ref | tee output_ref.txt
 	vvp -N testbench.vvp | tee output_sim.txt
 	diff -u output_ref.txt output_sim.txt
 
 spike: riscv-fesvr/build.ok riscv-isa-sim/build.ok test_ref test.elf
 	./test_ref | tee output_ref.txt
-	LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike test.elf | tee output_spike.txt
+	LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike test.elf | tee output_sim.txt
-	diff -u output_ref.txt output_spike.txt
+	diff -u output_ref.txt output_sim.txt
 
 riscv-fesvr/build.ok:
 	rm -rf riscv-fesvr
@@ -31,6 +51,10 @@ testbench.vvp: testbench.v ../../picorv32.v
 	iverilog -o testbench.vvp testbench.v ../../picorv32.v
 	chmod -x testbench.vvp
 
+obj_dir/Vtestbench: testbench.v testbench.cc ../../picorv32.v
+	verilator --exe -Wno-fatal --cc --top-module testbench testbench.v ../../picorv32.v testbench.cc
+	$(MAKE) -C obj_dir -f Vtestbench.mk
+
 test.hex: test.elf
 	$(RISCV_TOOLS_PREFIX)objcopy -O verilog test.elf test.hex
 
@@ -53,11 +77,11 @@ test.c:
 	csmith --no-packed-struct -o test.c
 
 clean:
-	rm -f platform.info test.c test.ld test.elf test.hex test_ref testbench.vvp testbench.vcd
+	rm -rf platform.info test.c test.ld test.elf test.hex test_ref obj_dir
-	rm -f output_ref.txt output_sim.txt output_spike.txt
+	rm -rf testbench.vvp testbench.vcd output_ref.txt output_sim.txt
 
 mrproper: clean
 	rm -rf riscv-fesvr riscv-isa-sim
 
-.PHONY: run spike clean mrproper
+.PHONY: help loop verilator iverilog spike clean mrproper
 

scripts/csmith/testbench.cc

@@ -0,0 +1,18 @@
+#include "Vtestbench.h"
+#include "verilated.h"
+
+int main(int argc, char **argv, char **env)
+{
+	Verilated::commandArgs(argc, argv);
+	Vtestbench* top = new Vtestbench;
+
+	top->clk = 0;
+	while (!Verilated::gotFinish()) {
+		top->clk = !top->clk;
+		top->eval();
+	}
+
+	delete top;
+	exit(0);
+}
+

scripts/csmith/testbench.v

@@ -1,19 +1,30 @@
 `timescale 1 ns / 1 ps
 
-module testbench;
+module testbench (
+`ifdef VERILATOR
+	input clk
+`endif
+);
+`ifndef VERILATOR
 	reg clk = 1;
-	reg resetn = 0;
-	wire trap;
-
 	always #5 clk = ~clk;
+`endif
+
+	reg resetn = 0;
+	integer resetn_cnt = 0;
+	wire trap;
 
 	initial begin
 		// $dumpfile("testbench.vcd");
 		// $dumpvars(0, testbench);
-		repeat (100) @(posedge clk);
-		resetn <= 1;
 	end
 
+	always @(posedge clk) begin
+		if (resetn_cnt < 100)
+			resetn_cnt <= resetn_cnt + 1;
+		else
+			resetn <= 1;
+	end
 
 	wire mem_valid;
 	wire mem_instr;
@@ -53,7 +64,9 @@ module testbench;
 	always @(posedge clk) begin
 		if (mem_valid && mem_wstrb && mem_addr == 'h10000000) begin
 			$write("%c", mem_wdata[ 7: 0]);
+`ifndef VERILATOR
 			$fflush;
+`endif
 		end else begin
 			if (mem_valid && mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
 			if (mem_valid && mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
@@ -64,7 +77,7 @@ module testbench;
 
 	always @(posedge clk) begin
 		if (resetn && trap) begin
-			repeat (10) @(posedge clk);
+			// repeat (10) @(posedge clk);
 			// $display("TRAP");
 			$finish;
 		end