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Merge pull request #37 from open-design/20170315.testbenches 

20170315.testbenches
This commit is contained in:
Clifford Wolf 2017-03-15 11:30:19 +01:00 committed by GitHub
parent 726a76c1cc 8e55b93541
commit 22ee418a74
3 changed files with 19 additions and 20 deletions
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20
Makefile
View File

@ -11,7 +11,7 @@ TOOLCHAIN_PREFIX = $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)i/bin/riscv32-unknown-el
COMPRESSED_ISA = C
test: testbench.vvp firmware/firmware.hex
vvp -N testbench.vvp
vvp -N $<
test_vcd: testbench.vvp firmware/firmware.hex
vvp -N $< +vcd +trace +noerror
@ -35,29 +35,29 @@ check.smt2: picorv32.v
-p 'write_smt2 -wires check.smt2'
test_sp: testbench_sp.vvp firmware/firmware.hex
vvp -N testbench_sp.vvp
vvp -N $<
test_axi: testbench.vvp firmware/firmware.hex
vvp -N testbench.vvp +axi_test
vvp -N $< +axi_test
test_synth: testbench_synth.vvp firmware/firmware.hex
vvp -N testbench_synth.vvp
vvp -N $<
testbench.vvp: testbench.v picorv32.v
iverilog -o testbench.vvp $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DRISCV_FORMAL testbench.v picorv32.v
chmod -x testbench.vvp
iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DRISCV_FORMAL $^
chmod -x $@
testbench_wb.vvp: testbench_wb.v picorv32.v
iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DRISCV_FORMAL $^
chmod -x $@
testbench_sp.vvp: testbench.v picorv32.v
iverilog -o testbench_sp.vvp $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DRISCV_FORMAL -DSP_TEST testbench.v picorv32.v
chmod -x testbench_sp.vvp
iverilog -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DRISCV_FORMAL -DSP_TEST $^
chmod -x $@
testbench_synth.vvp: testbench.v synth.v
iverilog -o testbench_synth.vvp -DSYNTH_TEST testbench.v synth.v
chmod -x testbench_synth.vvp
iverilog -o $@ -DSYNTH_TEST $^
chmod -x $@
synth.v: picorv32.v scripts/yosys/synth_sim.ys
yosys -qv3 -l synth.log scripts/yosys/synth_sim.ys

4
testbench.v
View File

@ -176,7 +176,7 @@ module picorv32_wrapper #(
reg [1023:0] firmware_file;
initial begin
if(!$value$plusargs("firmware=%s", firmware_file))
if (!$value$plusargs("firmware=%s", firmware_file))
firmware_file = "firmware/firmware.hex";
$readmemh(firmware_file, mem.memory);
end
@ -300,7 +300,7 @@ module axi4_memory #(
end endtask
task handle_axi_rvalid; begin
if(verbose)
if (verbose)
$display("RD: ADDR=%08x DATA=%08x%s", latched_raddr, memory[latched_raddr >> 2], latched_rinsn ? " INSN" : "");
if (latched_raddr < 64*1024) begin
mem_axi_rdata <= memory[latched_raddr >> 2];

15
testbench_wb.v
View File

@ -294,14 +294,13 @@ module wb_ram #(
reg [31:0] mem [0:depth/4-1] /* verilator public */;
always @(posedge wb_clk_i) begin
if (adr_r[aw-1:0] == 32'h1000_0000 && wb_stb_i && !wb_ack_o)
begin
$write("%c", wb_dat_i[7:0]);
end else
if (adr_r[aw-1:0] == 32'h2000_0000 && wb_stb_i && !wb_ack_o) begin
if (wb_dat_i[31:0] == 123456789)
tests_passed = 1;
end
if (ram_we)
if (adr_r[aw-1:0] == 32'h1000_0000)
$write("%c", wb_dat_i[7:0]);
else
if (adr_r[aw-1:0] == 32'h2000_0000)
if (wb_dat_i[31:0] == 123456789)
tests_passed = 1;
end
always @(posedge wb_clk_i) begin