Use RV32IC in scripts/torture/
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@ -41,7 +41,7 @@ tests/test_$(1).S: tests/generated.ok
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mv riscv-torture/output/test_$(1).S tests/
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tests/test_$(1).elf: tests/test_$(1).S
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riscv32-unknown-elf-gcc -m32 -ffreestanding -nostdlib -Wl,-Bstatic,-T,sections.lds -I. -o tests/test_$(1).elf tests/test_$(1).S
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riscv32-unknown-elf-gcc -m32 -march=RV32IC -ffreestanding -nostdlib -Wl,-Bstatic,-T,sections.lds -I. -o tests/test_$(1).elf tests/test_$(1).S
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tests/test_$(1).bin: tests/test_$(1).elf
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riscv32-unknown-elf-objcopy -O binary tests/test_$(1).elf tests/test_$(1).bin
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@ -15,7 +15,7 @@ fi
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## Compile test case and create reference
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riscv32-unknown-elf-gcc -m32 -ffreestanding -nostdlib -Wl,-Bstatic,-T,sections.lds -o test.elf test.S
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riscv32-unknown-elf-gcc -m32 -march=RV32IC -ffreestanding -nostdlib -Wl,-Bstatic,-T,sections.lds -o test.elf test.S
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LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike test.elf > test.ref
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riscv32-unknown-elf-objcopy -O binary test.elf test.bin
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python3 ../../firmware/makehex.py test.bin 4096 > test.hex
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@ -19,6 +19,7 @@ module testbench (
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reg [31:0] mem_rdata;
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picorv32 #(
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.COMPRESSED_ISA(1)
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) uut (
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.clk (clk ),
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.resetn (resetn ),
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