Makefile for Vivado scripts

scripts/vivado/.gitignore

@@ -1,4 +1,2 @@
-fsm_encoding.os
-synth_vivado.log
-synth_vivado_*.backup.log
-synth_vivado_syn.v
+synth_*.log
+synth_*.v

scripts/vivado/Makefile

@@ -0,0 +1,10 @@
+
+VIVADO = /opt/Xilinx/Vivado/2014.4/bin/vivado
+
+help:
+	@echo "Usage: make {synth_speed|synth_area|synth_soc}"
+
+synth_%:
+	$(VIVADO) -nojournal -log $@.log -mode batch -source $@.tcl
+	rm -rf .Xil fsm_encoding.os synth_*.backup.log
+

scripts/vivado/soc_top.v

@@ -1,6 +1,6 @@
 `timescale 1 ns / 1 ps
 
-module test_soc (
+module soc_top (
 	input         clk,
 	input         resetn,
 	output        trap,

scripts/vivado/synth_area.tcl

@@ -0,0 +1,14 @@
+
+read_verilog ../../picorv32.v
+read_xdc synth_area.xdc
+
+synth_design -part xc7a15t-csg324 -top picorv32_axi
+opt_design
+place_design
+route_design
+
+report_utilization
+report_timing
+
+write_verilog -force synth_area.v
+

scripts/vivado/synth_area.xdc

@@ -0,0 +1 @@
+create_clock -period 20.00 [get_ports clk]

scripts/vivado/synth_soc.tcl

@@ -0,0 +1,15 @@
+
+read_verilog soc_top.v
+read_verilog ../../picorv32.v
+read_xdc synth_soc.xdc
+
+synth_design -part xc7a15t-csg324 -top soc_top
+opt_design
+place_design
+route_design
+
+report_utilization
+report_timing
+
+write_verilog -force synth_soc.v
+

scripts/vivado/synth_soc.xdc

@@ -0,0 +1 @@
+create_clock -period 5.00 [get_ports clk]

scripts/vivado/synth_speed.tcl

@@ -0,0 +1,14 @@
+
+read_verilog ../../picorv32.v
+read_xdc synth_speed.xdc
+
+synth_design -part xc7a15t-csg324 -top picorv32_axi
+opt_design
+place_design
+route_design
+
+report_utilization
+report_timing
+
+write_verilog -force synth_speed.v
+

scripts/vivado/synth_vivado.tcl

@@ -1,18 +0,0 @@
-
-# vivado -nojournal -log synth_vivado.log -mode batch -source synth_vivado.tcl
-
-read_verilog synth_vivado_soc.v
-read_verilog ../../picorv32.v
-read_xdc synth_vivado.xdc
-
-synth_design -part xc7a15t-csg324 -top picorv32_axi
-# synth_design -part xc7a15t-csg324 -top test_soc
-opt_design
-place_design
-route_design
-
-report_utilization
-report_timing
-
-write_verilog -force synth_vivado_syn.v
-