Improvements in scripts/csmith/

This commit is contained in:
Clifford Wolf 2016-05-05 02:00:26 +02:00
parent 211fb521a8
commit 264a239a28
4 changed files with 77 additions and 61 deletions

View File

@ -7,30 +7,28 @@ SHELL = /bin/bash
help: help:
@echo "Usage: make { loop | verilator | iverilog | spike }" @echo "Usage: make { loop | verilator | iverilog | spike }"
loop: loop: riscv-fesvr/build.ok riscv-isa-sim/build.ok obj_dir/Vtestbench
+set -e; x() { echo "$$*" >&2; "$$@"; }; while true; do \ +set -e; x() { echo "$$*" >&2; "$$@"; }; i=1; j=1; while true; do echo; echo; \
echo; echo; rm -f output_ref.txt output_sim.txt; \ echo "---------------- $$((i++)) ($$j) ----------------"; \
echo "-----------------------------------------"; \ x rm -f test.hex test.elf test.c test_ref test.ld output_ref.txt output_sim.txt; \
x rm -f test.hex test.elf test.c test_ref test.ld; \ x make spike test.hex || { echo SKIP; continue; }; x rm -f output_sim.txt; \
x $(MAKE) test_ref test.hex obj_dir/Vtestbench; \ x obj_dir/Vtestbench | grep -v '$$finish' > output_sim.txt; \
x timeout 1 ./test_ref > >( tee output_ref.txt; ) || { echo TIMEOUT; continue; }; \ x diff -u output_ref.txt output_sim.txt; echo OK; ! ((j++)); \
x obj_dir/Vtestbench > >( tee /dev/stderr | grep -v '$$finish' > output_sim.txt; ); \
sleep 1; x diff -u output_ref.txt output_sim.txt; echo "OK."; \
done done
verilator: test_ref test.hex obj_dir/Vtestbench verilator: test_ref test.hex obj_dir/Vtestbench
./test_ref | tee output_ref.txt timeout 2 ./test_ref > output_ref.txt && cat output_ref.txt
obj_dir/Vtestbench | grep -v '$$finish' | tee output_sim.txt obj_dir/Vtestbench | grep -v '$$finish' > output_sim.txt
diff -u output_ref.txt output_sim.txt diff -u output_ref.txt output_sim.txt
iverilog: test_ref test.hex testbench.vvp iverilog: test_ref test.hex testbench.vvp
./test_ref | tee output_ref.txt timeout 2 ./test_ref > output_ref.txt && cat output_ref.txt
vvp -N testbench.vvp | tee output_sim.txt vvp -N testbench.vvp > output_sim.txt
diff -u output_ref.txt output_sim.txt diff -u output_ref.txt output_sim.txt
spike: riscv-fesvr/build.ok riscv-isa-sim/build.ok test_ref test.elf spike: riscv-fesvr/build.ok riscv-isa-sim/build.ok test_ref test.elf
./test_ref | tee output_ref.txt timeout 2 ./test_ref > output_ref.txt && cat output_ref.txt
LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike test.elf | tee output_sim.txt LD_LIBRARY_PATH="./riscv-isa-sim:./riscv-fesvr" ./riscv-isa-sim/spike test.elf > output_sim.txt
diff -u output_ref.txt output_sim.txt diff -u output_ref.txt output_sim.txt
riscv-fesvr/build.ok: riscv-fesvr/build.ok:
@ -42,8 +40,7 @@ riscv-isa-sim/build.ok: riscv-fesvr/build.ok
rm -rf riscv-isa-sim rm -rf riscv-isa-sim
git clone https://github.com/riscv/riscv-isa-sim.git riscv-isa-sim git clone https://github.com/riscv/riscv-isa-sim.git riscv-isa-sim
cd riscv-isa-sim && git checkout 10ae74e cd riscv-isa-sim && git checkout 10ae74e
cd riscv-isa-sim && patch -p1 < ../riscv-isa-sim-exit.diff cd riscv-isa-sim && patch -p1 < ../riscv-isa-sim.diff
cd riscv-isa-sim && patch -p1 < ../riscv-isa-sim-console.diff
cd riscv-isa-sim && LDFLAGS="-L../riscv-fesvr" ./configure --with-isa=RV32IMC cd riscv-isa-sim && LDFLAGS="-L../riscv-fesvr" ./configure --with-isa=RV32IMC
+cd riscv-isa-sim && ln -s ../riscv-fesvr/fesvr . && make && touch build.ok +cd riscv-isa-sim && ln -s ../riscv-fesvr/fesvr . && make && touch build.ok
@ -75,6 +72,7 @@ test.c:
echo "integer size = 4" > platform.info echo "integer size = 4" > platform.info
echo "pointer size = 4" >> platform.info echo "pointer size = 4" >> platform.info
csmith --no-packed-struct -o test.c csmith --no-packed-struct -o test.c
gawk '/Seed:/ {print$$2,$$3;}' test.c
clean: clean:
rm -rf platform.info test.c test.ld test.elf test.hex test_ref obj_dir rm -rf platform.info test.c test.ld test.elf test.hex test_ref obj_dir

View File

@ -1,14 +0,0 @@
diff --git a/riscv/mmu.h b/riscv/mmu.h
index b9948c5..bee1f8b 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -67,7 +67,8 @@ public:
if (addr & (sizeof(type##_t)-1)) \
throw trap_store_address_misaligned(addr); \
reg_t vpn = addr >> PGSHIFT; \
- if (likely(tlb_store_tag[vpn % TLB_ENTRIES] == vpn)) \
+ if (addr == 0x10000000) putchar(val), fflush(stdout); \
+ else if (likely(tlb_store_tag[vpn % TLB_ENTRIES] == vpn)) \
*(type##_t*)(tlb_data[vpn % TLB_ENTRIES] + addr) = val; \
else \
store_slow_path(addr, sizeof(type##_t), (const uint8_t*)&val); \

View File

@ -1,30 +0,0 @@
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -201,9 +201,10 @@ void processor_t::set_privilege(reg_t prv)
void processor_t::take_trap(trap_t& t, reg_t epc)
{
- if (debug)
+ // if (debug)
fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
id, t.name(), epc);
+ exit(1);
// by default, trap to M-mode, unless delegated to S-mode
reg_t bit = t.cause();
--- a/riscv/insns/c_ebreak.h
+++ b/riscv/insns/c_ebreak.h
@@ -1,2 +1,6 @@
require_extension('C');
+
+fprintf(stderr, "sbreak\n");
+exit(0);
+
throw trap_breakpoint();
--- a/riscv/insns/sbreak.h
+++ b/riscv/insns/sbreak.h
@@ -1 +1,4 @@
+fprintf(stderr, "sbreak\n");
+exit(0);
+
throw trap_breakpoint();

View File

@ -0,0 +1,62 @@
diff --git a/riscv/execute.cc b/riscv/execute.cc
index 5c3fdf7..4d914b3 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -124,6 +124,10 @@ miss:
}
state.minstret += instret;
+ if (state.minstret > 1000000) {
+ printf("Reached limit of 1000000 instructions.\n");
+ exit(0);
+ }
n -= instret;
}
}
diff --git a/riscv/insns/c_ebreak.h b/riscv/insns/c_ebreak.h
index a17200f..f06d8d9 100644
--- a/riscv/insns/c_ebreak.h
+++ b/riscv/insns/c_ebreak.h
@@ -1,2 +1,4 @@
require_extension('C');
+
+exit(0);
throw trap_breakpoint();
diff --git a/riscv/insns/sbreak.h b/riscv/insns/sbreak.h
index c22776c..d38bd22 100644
--- a/riscv/insns/sbreak.h
+++ b/riscv/insns/sbreak.h
@@ -1 +1,2 @@
+exit(0);
throw trap_breakpoint();
diff --git a/riscv/mmu.h b/riscv/mmu.h
index b9948c5..bee1f8b 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -67,7 +67,8 @@ public:
if (addr & (sizeof(type##_t)-1)) \
throw trap_store_address_misaligned(addr); \
reg_t vpn = addr >> PGSHIFT; \
- if (likely(tlb_store_tag[vpn % TLB_ENTRIES] == vpn)) \
+ if (addr == 0x10000000) putchar(val), fflush(stdout); \
+ else if (likely(tlb_store_tag[vpn % TLB_ENTRIES] == vpn)) \
*(type##_t*)(tlb_data[vpn % TLB_ENTRIES] + addr) = val; \
else \
store_slow_path(addr, sizeof(type##_t), (const uint8_t*)&val); \
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 3b834c5..f407543 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -201,9 +201,9 @@ void processor_t::set_privilege(reg_t prv)
void processor_t::take_trap(trap_t& t, reg_t epc)
{
- if (debug)
- fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
- id, t.name(), epc);
+ printf("core %3d: exception %s, epc 0x%016" PRIx64 "\n",
+ id, t.name(), epc);
+ exit(0);
// by default, trap to M-mode, unless delegated to S-mode
reg_t bit = t.cause();