colin
/
picorv32
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Minor README changes

This commit is contained in:
Clifford Wolf 2015-06-26 10:51:15 +02:00
parent 1a664f9b97
commit 266ff03539
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
README.md
View File

@ -14,7 +14,7 @@ Features and Typical Applications:
----------------------------------
- Small (~1000 LUTs in a 7-Series Xilinx FGPA)
- High fMAX (>250 MHz on 7-Series Xilinx FGPAs)
- High fMAX (~250 MHz on 7-Series Xilinx FGPAs)
- Selectable native memory interface or AXI4-Lite master
This CPU is meant to be used as auxiliary processor in FPGA designs and ASICs. Due
@ -154,7 +154,7 @@ The IRQs 0-2 can be triggered internally and have the following meaning:
The core has 4 additional 32-bit registers `q0 .. q3` that are used for IRQ
handling. When an IRQ triggers, the register `q0` contains the return address
and `q1` contains a bitmask of all active IRQs. I.e. one call to the interrupt
and `q1` contains a bitmask of all active IRQs. This means one call to the interrupt
handler might need to service one than more IRQ when more than one bit is set
in `q1`.