Move debug from core to test bench.

picorv32.v

@@ -24,10 +24,6 @@
 
 `timescale 1 ns / 1 ps
 // `default_nettype none
-// `define DEBUGNETS
-// `define DEBUGREGS
-// `define DEBUGASM
-// `define DEBUG
 
 `ifdef DEBUG
 `define debug(debug_command) debug_command
@@ -86,7 +82,13 @@ module picorv32 #(
 
     // Trace Interface
     output reg        trace_valid,
-    output reg [35:0] trace_data
+    output reg [35:0] trace_data,
+
+    // IF DEBUG
+    output reg fetch_next,
+    output reg [31:0] dbg_insn_opcode,
+    output reg [31:0] dbg_insn_addr,
+    output reg [63:0] dbg_ascii_instr
 );
   localparam integer irq_timer = 0;
   localparam integer irq_ebreak = 1;
@@ -104,8 +106,6 @@ module picorv32 #(
   reg [4:0] reg_sh;
 
   reg [31:0] next_insn_opcode;
-  reg [31:0] dbg_insn_opcode;
-  reg [31:0] dbg_insn_addr;
 
   wire dbg_mem_valid = mem_valid;
   wire dbg_mem_instr = mem_instr;
@@ -400,7 +400,7 @@ module picorv32 #(
 
   reg [63:0] new_ascii_instr;
 
-  reg [63:0] dbg_ascii_instr;
+
   reg [31:0] dbg_insn_imm;
   reg [4:0] dbg_insn_rs1;
   reg [4:0] dbg_insn_rs2;
@@ -475,7 +475,6 @@ module picorv32 #(
   reg [4:0] q_insn_rs1;
   reg [4:0] q_insn_rs2;
   reg [4:0] q_insn_rd;
-  reg dbg_next;
 
   wire launch_next_insn;
   reg dbg_valid_insn;
@@ -494,7 +493,7 @@ module picorv32 #(
     q_insn_rs1 <= dbg_insn_rs1;
     q_insn_rs2 <= dbg_insn_rs2;
     q_insn_rd <= dbg_insn_rd;
-    dbg_next <= launch_next_insn;
+    fetch_next <= launch_next_insn;
 
     if (!resetn || trap) dbg_valid_insn <= 0;
     else if (launch_next_insn) dbg_valid_insn <= 1;
@@ -522,7 +521,7 @@ module picorv32 #(
     dbg_insn_rs2 = q_insn_rs2;
     dbg_insn_rd = q_insn_rd;
 
-    if (dbg_next) begin
+    if (fetch_next) begin
       if (decoder_pseudo_trigger_q) begin
         dbg_ascii_instr = cached_ascii_instr;
         dbg_insn_imm = cached_insn_imm;
@@ -542,36 +541,6 @@ module picorv32 #(
     end
   end
 
-`ifdef DEBUGASM
-  always @(posedge clk) begin
-    if (dbg_next) begin
-      $display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode,
-               dbg_ascii_instr ? dbg_ascii_instr : "*");
-    end
-  end
-`endif
-
-`ifdef DEBUG
-  always @(posedge clk) begin
-    if (dbg_next) begin
-      if (&dbg_insn_opcode[1:0])
-        $display(
-            "DECODE: 0x%08x 0x%08x %-0s",
-            dbg_insn_addr,
-            dbg_insn_opcode,
-            dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
-        );
-      else
-        $display(
-            "DECODE: 0x%08x     0x%04x %-0s",
-            dbg_insn_addr,
-            dbg_insn_opcode[15:0],
-            dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
-        );
-    end
-  end
-`endif
-
   always @(posedge clk) begin
     is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
     is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
@@ -966,11 +935,7 @@ module picorv32 #(
             latched_branch: begin
               current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
               `debug($display(
-                     "ST_RD:  %2d 0x%08x, BRANCH 0x%08x",
+                     "ST_RD:  %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + 4, current_pc);)
-                     latched_rd,
-                     reg_pc + 4,
-                     current_pc
-                     );)
             end
             latched_store && !latched_branch: begin
               `debug($display("ST_RD:  %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out
@@ -1007,7 +972,7 @@ module picorv32 #(
           latched_rd <= decoded_rd;
 
           if (((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
-            irq_state <= irq_state == 2'b00 ? 2'b01 : irq_state == 2'b01 ? 2'b10 : 2'b00;
+            irq_state  <= irq_state == 2'b00 ? 2'b01 : irq_state == 2'b01 ? 2'b10 : 2'b00;
             latched_rd <= irqregs_offset | irq_state[0];
           end else if ((decoder_trigger || do_waitirq) && instr_waitirq) begin
             if (irq_pending) begin

testbench_wb.v

@@ -98,6 +98,11 @@ module picorv32_wb #(
   wire [31:0] mem_la_wdata;
   wire [ 3:0] mem_la_wstrb;
 
+  // IF DEBUG
+  wire        fetch_next;
+  wire [31:0] dbg_insn_opcode;
+  wire [31:0] dbg_insn_addr;
+  wire [63:0] dbg_ascii_instr;
 
   wire        clk;
   wire        resetn;
@@ -134,7 +139,12 @@ module picorv32_wb #(
       .eoi         (eoi),
 
       .trace_valid(trace_valid),
-      .trace_data (trace_data)
+      .trace_data (trace_data),
+
+      .fetch_next(fetch_next),
+      .dbg_insn_opcode(dbg_insn_opcode),
+      .dbg_insn_addr(dbg_insn_addr),
+      .dbg_ascii_instr(dbg_ascii_instr)
   );
 
 
@@ -142,9 +152,10 @@ module picorv32_wb #(
 
   assign mem_ready = 1;
 
-  integer fconsole;
+  integer fconsole, fif;
   initial begin
     fconsole = $fopen("console.log", "w");
+    fif = $fopen("if.log", "w");
   end
 
   always @(posedge clk) begin
@@ -169,4 +180,26 @@ module picorv32_wb #(
       endcase
     end
   end
+
+  always @(posedge clk) begin
+    if (fetch_next) begin
+      if (&dbg_insn_opcode[1:0])
+        $fwrite(
+            fif,
+            "DECODE: 0x%08x 0x%08x %-0s\n",
+            dbg_insn_addr,
+            dbg_insn_opcode,
+            dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
+        );
+      else
+        $fwrite(
+            fif,
+            "DECODE: 0x%08x     0x%04x %-0s\n",
+            dbg_insn_addr,
+            dbg_insn_opcode[15:0],
+            dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"
+        );
+    end
+  end
+
 endmodule