Merge pull request #39 from open-design/20170324.wishbone
testbench_wb.v: drop unused stuff
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Clifford Wolf
GitHub
commit
2c6cbcf72f
107
testbench_wb.v
107
testbench_wb.v
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@ -81,13 +81,8 @@ module picorv32_wrapper #(
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wire wb_m2s_we;
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wire wb_m2s_cyc;
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wire wb_m2s_stb;
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//wire [2:0] wb_m2s_cti;
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reg [2:0] wb_m2s_cti = 3'b000;
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wire [1:0] wb_m2s_bte;
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wire [31:0] wb_s2m_dat;
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wire wb_s2m_ack;
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wire wb_s2m_err;
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wire wb_s2m_rty;
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wb_ram #(
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.depth (16384 * 4),
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@ -104,10 +99,7 @@ module picorv32_wrapper #(
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.wb_dat_o(wb_s2m_dat),
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.wb_ack_o(wb_s2m_ack),
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.wb_sel_i(wb_m2s_sel),
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.wb_cti_i(wb_m2s_cti),
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.wb_bte_i(wb_m2s_bte),
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.wb_we_i(wb_m2s_we),
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.wb_err_o(),
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.tests_passed(tests_passed)
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);
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@ -166,126 +158,49 @@ module picorv32_wrapper #(
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endmodule
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module wb_ram #(
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//Wishbone parameters
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parameter dw = 32,
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//Memory parameters
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parameter depth = 256,
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parameter aw = 32,
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parameter memfile = "",
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parameter VERBOSE = 0
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) (
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input wb_clk_i,
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input wb_rst_i,
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input [aw-1:0] wb_adr_i,
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input [dw-1:0] wb_dat_i,
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input [31:0] wb_adr_i,
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input [31:0] wb_dat_i,
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input [3:0] wb_sel_i,
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input wb_we_i,
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input [1:0] wb_bte_i,
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input [2:0] wb_cti_i,
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input wb_cyc_i,
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input wb_stb_i,
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output reg wb_ack_o,
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output wb_err_o,
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output reg [dw-1:0] wb_dat_o,
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output reg [31:0] wb_dat_o,
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output reg tests_passed
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);
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localparam CLASSIC_CYCLE = 1'b0;
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localparam BURST_CYCLE = 1'b1;
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localparam READ = 1'b0;
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localparam WRITE = 1'b1;
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localparam [2:0]
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CTI_CLASSIC = 3'b000,
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CTI_CONST_BURST = 3'b001,
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CTI_INC_BURST = 3'b010,
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CTI_END_OF_BURST = 3'b111;
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localparam [1:0]
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BTE_LINEAR = 2'd0,
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BTE_WRAP_4 = 2'd1,
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BTE_WRAP_8 = 2'd2,
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BTE_WRAP_16 = 2'd3;
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function wb_is_last;
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input [2:0] cti;
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begin
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case (cti)
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CTI_CLASSIC : wb_is_last = 1'b1;
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CTI_CONST_BURST : wb_is_last = 1'b0;
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CTI_INC_BURST : wb_is_last = 1'b0;
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CTI_END_OF_BURST : wb_is_last = 1'b1;
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default : $display("%d : Illegal Wishbone B3 cycle type (%b)", $time, cti);
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endcase
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end
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endfunction
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function [31:0] wb_next_adr;
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input [31:0] adr_i;
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input [2:0] cti_i;
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input [2:0] bte_i;
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input integer dw;
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reg [31:0] adr;
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integer shift;
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begin
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shift = $clog2(dw/8);
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adr = adr_i >> shift;
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if (cti_i == CTI_INC_BURST)
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case (bte_i)
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BTE_LINEAR : adr = adr + 1;
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BTE_WRAP_4 : adr = {adr[31:2], adr[1:0]+2'd1};
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BTE_WRAP_8 : adr = {adr[31:3], adr[2:0]+3'd1};
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BTE_WRAP_16 : adr = {adr[31:4], adr[3:0]+4'd1};
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endcase // case (burst_type_i)
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wb_next_adr = adr << shift;
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end
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endfunction
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reg verbose;
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initial verbose = $test$plusargs("verbose") || VERBOSE;
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initial tests_passed = 0;
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reg [aw-1:0] adr_r;
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wire [aw-1:0] next_adr;
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reg [31:0] adr_r;
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wire valid = wb_cyc_i & wb_stb_i;
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reg valid_r;
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reg is_last_r;
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always @(posedge wb_clk_i)
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is_last_r <= wb_is_last(wb_cti_i);
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wire new_cycle = (valid & !valid_r) | is_last_r;
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assign next_adr = wb_next_adr(adr_r, wb_cti_i, wb_bte_i, dw);
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wire [aw-1:0] adr = new_cycle ? wb_adr_i : next_adr;
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always @(posedge wb_clk_i) begin
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adr_r <= adr;
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valid_r <= valid;
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adr_r <= wb_adr_i;
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// Ack generation
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wb_ack_o <= valid & (!((wb_cti_i == 3'b000) | (wb_cti_i == 3'b111)) | !wb_ack_o);
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wb_ack_o <= valid & !wb_ack_o;
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if (wb_rst_i)
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begin
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adr_r <= {aw{1'b0}};
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valid_r <= 1'b0;
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adr_r <= {32{1'b0}};
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wb_ack_o <= 1'b0;
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end
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end
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wire ram_we = wb_we_i & valid & wb_ack_o;
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assign wb_err_o = 1'b0;
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wire [aw-1:0] waddr = adr_r[aw-1:2];
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wire [aw-1:0] raddr = adr[aw-1:2];
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wire [31:0] waddr = adr_r[31:2];
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wire [31:0] raddr = wb_adr_i[31:2];
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wire [3:0] we = {4{ram_we}} & wb_sel_i;
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wire [$clog2(depth/4)-1:0] raddr2 = raddr[$clog2(depth/4)-1:0];
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@ -295,10 +210,10 @@ module wb_ram #(
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always @(posedge wb_clk_i) begin
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if (ram_we)
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if (adr_r[aw-1:0] == 32'h1000_0000)
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if (adr_r[31:0] == 32'h1000_0000)
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$write("%c", wb_dat_i[7:0]);
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else
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if (adr_r[aw-1:0] == 32'h2000_0000)
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if (adr_r[31:0] == 32'h2000_0000)
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if (wb_dat_i[31:0] == 123456789)
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tests_passed = 1;
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end
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