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Enable the use of 64-bit riscv tools 

Many Linux distributions now include the tools for RISC-V (for example
Ubuntu 20.04 has gcc-riscv64-unknown-elf) but in order for

  make TOOLCHAIN_PREFIX=riscv64-unknown-elf-

to work we need to be explicit about compiling for 32-bit.
This commit is contained in:
Tommy Thorn 2020-06-03 00:48:04 -07:00
parent f9b1beb4cf
commit 2cce6f4e8b
3 changed files with 10 additions and 7 deletions
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10
Makefile
View File

@ -107,19 +107,19 @@ firmware/firmware.bin: firmware/firmware.elf
chmod -x $@
firmware/firmware.elf: $(FIRMWARE_OBJS) $(TEST_OBJS) firmware/sections.lds
$(TOOLCHAIN_PREFIX)gcc -Os -ffreestanding -nostdlib -o $@ \
-Wl,-Bstatic,-T,firmware/sections.lds,-Map,firmware/firmware.map,--strip-debug \
$(TOOLCHAIN_PREFIX)gcc -Os -mabi=ilp32 -march=rv32im$(subst C,c,$(COMPRESSED_ISA)) -ffreestanding -nostdlib -o $@ \
-Wl,--build-id=none,-Bstatic,-T,firmware/sections.lds,-Map,firmware/firmware.map,--strip-debug \
$(FIRMWARE_OBJS) $(TEST_OBJS) -lgcc
chmod -x $@
firmware/start.o: firmware/start.S
$(TOOLCHAIN_PREFIX)gcc -c -march=rv32im$(subst C,c,$(COMPRESSED_ISA)) -o $@ $<
$(TOOLCHAIN_PREFIX)gcc -c -mabi=ilp32 -march=rv32im$(subst C,c,$(COMPRESSED_ISA)) -o $@ $<
firmware/%.o: firmware/%.c
$(TOOLCHAIN_PREFIX)gcc -c -march=rv32i$(subst C,c,$(COMPRESSED_ISA)) -Os --std=c99 $(GCC_WARNS) -ffreestanding -nostdlib -o $@ $<
$(TOOLCHAIN_PREFIX)gcc -c -mabi=ilp32 -march=rv32i$(subst C,c,$(COMPRESSED_ISA)) -Os --std=c99 $(GCC_WARNS) -ffreestanding -nostdlib -o $@ $<
tests/%.o: tests/%.S tests/riscv_test.h tests/test_macros.h
$(TOOLCHAIN_PREFIX)gcc -c -march=rv32im -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
$(TOOLCHAIN_PREFIX)gcc -c -mabi=ilp32 -march=rv32im -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
-DTEST_FUNC_TXT='"$(notdir $(basename $<))"' -DTEST_FUNC_RET=$(notdir $(basename $<))_ret $<
download-tools:

3
README.md
View File

@ -9,6 +9,9 @@ contains a built-in interrupt controller.
Tools (gcc, binutils, etc..) can be obtained via the [RISC-V Website](https://riscv.org/software-status/).
The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in `/opt/riscv32i[m][c]`. See
the [build instructions below](#building-a-pure-rv32i-toolchain) for details.
Many Linux distributions now include the tools for RISC-V (for example
Ubuntu 20.04 has `gcc-riscv64-unknown-elf`). To compile using those set
`TOOLCHAIN_PREFIX` accordingly (eg. `make TOOLCHAIN_PREFIX=riscv64-unknown-elf-`).
PicoRV32 is free and open hardware licensed under the [ISC license](http://en.wikipedia.org/wiki/ISC_license)
(a license that is similar in terms to the MIT license or the 2-clause BSD license).

4
picosoc/Makefile
View File

@ -40,7 +40,7 @@ hx8kdemo_sections.lds: sections.lds
$(CROSS)cpp -P -DHX8KDEMO -o $@ $^
hx8kdemo_fw.elf: hx8kdemo_sections.lds start.s firmware.c
$(CROSS)gcc $(CFLAGS) -DHX8KDEMO -march=rv32imc -Wl,-Bstatic,-T,hx8kdemo_sections.lds,--strip-debug -ffreestanding -nostdlib -o hx8kdemo_fw.elf start.s firmware.c
$(CROSS)gcc $(CFLAGS) -DHX8KDEMO -mabi=ilp32 -march=rv32imc -Wl,--build-id=none,-Bstatic,-T,hx8kdemo_sections.lds,--strip-debug -ffreestanding -nostdlib -o hx8kdemo_fw.elf start.s firmware.c
hx8kdemo_fw.hex: hx8kdemo_fw.elf
$(CROSS)objcopy -O verilog hx8kdemo_fw.elf hx8kdemo_fw.hex
@ -86,7 +86,7 @@ icebreaker_sections.lds: sections.lds
$(CROSS)cpp -P -DICEBREAKER -o $@ $^
icebreaker_fw.elf: icebreaker_sections.lds start.s firmware.c
$(CROSS)gcc $(CFLAGS) -DICEBREAKER -march=rv32ic -Wl,-Bstatic,-T,icebreaker_sections.lds,--strip-debug -ffreestanding -nostdlib -o icebreaker_fw.elf start.s firmware.c
$(CROSS)gcc $(CFLAGS) -DICEBREAKER -mabi=ilp32 -march=rv32ic -Wl,-Bstatic,-T,icebreaker_sections.lds,--strip-debug -ffreestanding -nostdlib -o icebreaker_fw.elf start.s firmware.c
icebreaker_fw.hex: icebreaker_fw.elf
$(CROSS)objcopy -O verilog icebreaker_fw.elf icebreaker_fw.hex