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Fixed "make timing" in dhrystone/

This commit is contained in:
Clifford Wolf 2016-04-13 19:52:52 +02:00
parent fd6e52adb0
commit 323d77ba5d
1 changed files with 3 additions and 2 deletions
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5
dhrystone/testbench.v
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@ -91,8 +91,9 @@ module testbench;
repeat (100000) @(posedge clk);
$finish;
end
always @(uut.count_instr[0]) begin
$display("## %-s %d", uut.ascii_instr ? uut.ascii_instr : "x", uut.count_cycle);
always @(posedge clk) begin
if (uut.decoder_trigger_q && !uut.decoder_pseudo_trigger_q)
$display("## %-s %d", uut.dbg_ascii_instr ? uut.dbg_ascii_instr : "x", uut.count_cycle);
end
`endif
endmodule