Fix indenting in wishbone code

picorv32.v

@@ -2690,9 +2690,8 @@ module picorv32_wb #(
 	wire we;
 	assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
 
-	always @(posedge wb_clk_i)
+	always @(posedge wb_clk_i) begin
-	if (wb_rst_i)
+		if (wb_rst_i) begin
-	begin
 			wbm_adr_o <= 0;
 			wbm_dat_o <= 0;
 			wbm_we_o <= 0;
@@ -2700,13 +2699,10 @@ module picorv32_wb #(
 			wbm_stb_o <= 0;
 			wbm_cyc_o <= 0;
 			state <= IDLE;
-	end
+		end else begin
-	else
-	begin
 			case (state)
-		IDLE:
+				IDLE: begin
-			if (mem_valid)
+					if (mem_valid) begin
-			begin
 						wbm_adr_o <= mem_addr;
 						wbm_dat_o <= mem_wdata;
 						wbm_we_o <= we;
@@ -2715,18 +2711,16 @@ module picorv32_wb #(
 						wbm_stb_o <= 1'b1;
 						wbm_cyc_o <= 1'b1;
 						state <= WBSTART;
-			end
+					end else begin
-			else
-			begin
 						mem_ready <= 1'b0;
 
 						wbm_stb_o <= 1'b0;
 						wbm_cyc_o <= 1'b0;
 						wbm_we_o <= 1'b0;
 					end
-		WBSTART:
+				end
-			if (wbm_ack_i)
+				WBSTART:begin
-			begin
+					if (wbm_ack_i) begin
 						mem_rdata <= wbm_dat_i;
 						mem_ready <= 1'b1;
 
@@ -2736,16 +2730,15 @@ module picorv32_wb #(
 						wbm_cyc_o <= 1'b0;
 						wbm_we_o <= 1'b0;
 					end
-
+				end
-		WBEND:
+				WBEND: begin
-			begin
 					mem_ready <= 1'b0;
 
 					state <= IDLE;
 				end
-
 				default:
 					state <= IDLE;
 			endcase
 		end
+	end
 endmodule

testbench_wb.v

@@ -93,8 +93,7 @@ wire wb_s2m_rty;
 		.depth (16384 * 4),
 		.memfile ("firmware/firmware.hex"),
 		.VERBOSE (VERBOSE)
-	)
+	) ram ( // Wishbone interface
-	ram (// Wishbone interface
 		.wb_clk_i(wb_clk),
 		.wb_rst_i(wb_rst),
 
@@ -166,16 +165,15 @@ wire wb_s2m_rty;
 	end
 endmodule
 
-module wb_ram
+module wb_ram #(
-	#(//Wishbone parameters
+	//Wishbone parameters
 	parameter dw = 32,
 	//Memory parameters
 	parameter depth = 256,
 	parameter aw = 32,
 	parameter memfile = "",
 	parameter VERBOSE = 0
-	)
+) (
-	(
 	input wb_clk_i,
 	input wb_rst_i,
 
@@ -269,8 +267,7 @@ endfunction
 
 	wire [aw-1:0] adr = new_cycle ? wb_adr_i : next_adr;
 
-	always @(posedge wb_clk_i)
+	always @(posedge wb_clk_i) begin
-	begin
 		adr_r <= adr;
 		valid_r <= valid;
 		// Ack generation
@@ -308,9 +305,7 @@ endfunction
 	end
 
 	always @(posedge wb_clk_i) begin
-
+		if (waddr2 < 64 * 1024 / 4) begin
-		if (waddr2 < 64 * 1024 / 4)
-		begin
 			if (we[0])
 				mem[waddr2][7:0] <= wb_dat_i[7:0];
 
@@ -336,11 +331,8 @@ endfunction
 		wb_dat_o <= mem[raddr2];
 	end
 
-	generate
+	initial begin
-		initial
+		if (memfile != "")
-		if (memfile != "") begin
 			$readmemh(memfile, mem);
 	end
-	endgenerate
-
 endmodule