Merge pull request #94 from hutch31/master
Added new testbench and linker file for ROM load
This commit is contained in:
Clifford Wolf
GitHub
commit
3a6ac16259
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@ -0,0 +1,11 @@
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firmware.d
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firmware.elf
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firmware.hex
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firmware32.hex
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firmware.o
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firmware_addr.txt
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firmware_dbg.v
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syscalls.o
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testbench.vvp
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testbench.vcd
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start.elf
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ifndef RISCV_TOOLS_PREFIX
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RISCV_TOOLS_PREFIX = /opt/riscv32ic/bin/riscv32-unknown-elf-
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endif
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CXX = $(RISCV_TOOLS_PREFIX)g++ -march=rv32i
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CC = $(RISCV_TOOLS_PREFIX)gcc -march=rv32i
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AS = $(RISCV_TOOLS_PREFIX)gcc -march=rv32i
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CXXFLAGS = -MD -Os -Wall -std=c++11
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CCFLAGS = -MD -Os -Wall
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#LDFLAGS = -Wl,--gc-sections,--no-relax
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LDFLAGS = -Wl,--gc-sections
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LDLIBS =
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test: testbench.vvp firmware32.hex
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vvp -l testbench.log -N testbench.vvp
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testbench.vvp: testbench.v ../../picorv32.v firmware_dbg.v
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iverilog -o testbench.vvp testbench.v ../../picorv32.v
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chmod -x testbench.vvp
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firmware32.hex: firmware.elf hex8tohex32.py
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$(RISCV_TOOLS_PREFIX)objcopy -O verilog firmware.elf firmware.tmp
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python3 hex8tohex32.py firmware.tmp > firmware32.hex
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firmware_dbg.v: firmware.map
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python3 map2debug.py
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start.o: start.S
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$(CC) -c -nostdlib start.S $(LDLIBS)
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firmware.elf: firmware.o syscalls.o start.o
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$(CC) $(LDFLAGS),-Map=firmware.map -o $@ $^ -T sections.ld $(LDLIBS)
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chmod -x firmware.elf
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clean:
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rm -f *.o *.d *.tmp start.elf
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rm -f firmware.elf firmware.hex firmware32.hex
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rm -f testbench.vvp testbench.vcd
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-include *.d
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.PHONY: test clean
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#include <stdio.h>
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#include <stdlib.h>
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int x1 = 1000;
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int x2 = 2000;
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void main()
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{
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int z;
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x1 = 50;
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x2 = 50;
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printf("hello\n");
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z = (x1 + x2);
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if (z == 100)
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printf("TEST PASSED\n");
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else
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printf("TEST FAILED, z=%d\n", z);
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exit(0);
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}
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#!/usr/bin/env python3
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import fileinput
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import itertools
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ptr = 0
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data = []
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def write_data():
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if len(data) != 0:
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print("@%08x" % (ptr >> 2))
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while len(data) % 4 != 0:
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data.append(0)
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for word_bytes in zip(*([iter(data)]*4)):
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print("".join(["%02x" % b for b in reversed(word_bytes)]))
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for line in fileinput.input():
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if line.startswith("@"):
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addr = int(line[1:], 16)
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if addr > ptr+4:
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write_data()
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ptr = addr
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data = []
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while ptr % 4 != 0:
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data.append(0)
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ptr -= 1
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else:
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while ptr + len(data) < addr:
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data.append(0)
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else:
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data += [int(tok, 16) for tok in line.split()]
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write_data()
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#!/usr/bin/env python3
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import re
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symbol = re.compile("\s*0x([0-9a-f]+)\s+([\w_]+)")
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symbol_map = {}
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with open("firmware.map", "r") as fh:
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for fd in fh:
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sym = symbol.match(fd)
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if (sym):
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addr = int(sym.group(1), 16)
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symbol_map[addr] = sym.group(2)
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with open("firmware_dbg.v", "w") as fh:
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for k, v in symbol_map.items():
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fh.write("`define C_SYM_{1:s} 32'h{0:08x}\n".format(k, v.upper()))
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fh.write(" task firmware_dbg;\n")
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fh.write(" input [31:0] addr;\n");
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fh.write(" begin\n");
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fh.write(" case (addr)\n");
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for k, v in symbol_map.items():
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fh.write(" 32'h{0:08x} : $display(\"%t: FCALL: {1:s}\", $time);\n".format(k, v))
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fh.write(" endcase\n");
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fh.write(" end\n");
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fh.write(" endtask\n");
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with open("firmware_addr.txt", "w") as fh:
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for k, v in symbol_map.items():
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fh.write("{0:08x} {1:s}\n".format(k,v))
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@ -0,0 +1,45 @@
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/*
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This is free and unencumbered software released into the public domain.
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Anyone is free to copy, modify, publish, use, compile, sell, or
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distribute this software, either in source code form or as a compiled
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binary, for any purpose, commercial or non-commercial, and by any
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means.
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*/
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/* starting address needs to be > 0 due to known bug in RISCV/GNU linker */
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MEMORY {
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rom(rwx) : ORIGIN = 0x00000100, LENGTH = 63k
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ram(rwx) : ORIGIN = 0x00020000, LENGTH = 16k
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}
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ENTRY(_pvstart);
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SECTIONS {
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.rom : {
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_pvstart*(.text);
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start*(.text);
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. = 0x100;
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. = ALIGN(4);
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*(.text);
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} > rom
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.data : {
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_data_lma = LOADADDR(.data);
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_data = .;
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__global_pointer$ = . ;
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*(.data .data.* )
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*(.sdata .sdata.*)
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. = ALIGN(4);
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_edata = .;
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} >ram AT>rom
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.bss : {
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_bss_start = .;
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*(.bss .bss.*)
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. = ALIGN(4);
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_bss_end = .;
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_end = .;
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} >ram
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}
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.section .text
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.global _start
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.global _pvstart
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_pvstart:
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/* zero-initialize all registers */
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addi x1, zero, 0
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addi x2, zero, 0
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addi x3, zero, 0
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addi x4, zero, 0
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addi x5, zero, 0
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addi x6, zero, 0
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addi x7, zero, 0
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addi x8, zero, 0
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addi x9, zero, 0
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addi x10, zero, 0
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addi x11, zero, 0
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addi x12, zero, 0
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addi x13, zero, 0
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addi x14, zero, 0
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addi x15, zero, 0
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addi x16, zero, 0
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addi x17, zero, 0
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addi x18, zero, 0
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addi x19, zero, 0
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addi x20, zero, 0
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addi x21, zero, 0
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addi x22, zero, 0
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addi x23, zero, 0
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addi x24, zero, 0
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addi x25, zero, 0
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addi x26, zero, 0
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addi x27, zero, 0
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addi x28, zero, 0
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addi x29, zero, 0
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addi x30, zero, 0
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addi x31, zero, 0
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/* set stack pointer */
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lui sp, %hi(4*1024*1024)
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addi sp, sp, %lo(4*1024*1024)
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/* push zeros on the stack for argc and argv */
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/* (stack is aligned to 16 bytes in riscv calling convention) */
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addi sp,sp,-16
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sw zero,0(sp)
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sw zero,4(sp)
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sw zero,8(sp)
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sw zero,12(sp)
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j _start
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// An extremely minimalist syscalls.c for newlib
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// Based on riscv newlib libgloss/riscv/sys_*.c
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// Written by Clifford Wolf.
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#include <sys/stat.h>
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#include <unistd.h>
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#include <errno.h>
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#define UNIMPL_FUNC(_f) ".globl " #_f "\n.type " #_f ", @function\n" #_f ":\n"
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asm (
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".text\n"
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".align 2\n"
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UNIMPL_FUNC(_open)
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UNIMPL_FUNC(_openat)
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UNIMPL_FUNC(_lseek)
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UNIMPL_FUNC(_stat)
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UNIMPL_FUNC(_lstat)
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UNIMPL_FUNC(_fstatat)
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UNIMPL_FUNC(_isatty)
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UNIMPL_FUNC(_access)
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UNIMPL_FUNC(_faccessat)
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UNIMPL_FUNC(_link)
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UNIMPL_FUNC(_unlink)
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UNIMPL_FUNC(_execve)
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UNIMPL_FUNC(_getpid)
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UNIMPL_FUNC(_fork)
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UNIMPL_FUNC(_kill)
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UNIMPL_FUNC(_wait)
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UNIMPL_FUNC(_times)
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UNIMPL_FUNC(_gettimeofday)
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UNIMPL_FUNC(_ftime)
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UNIMPL_FUNC(_utime)
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UNIMPL_FUNC(_chown)
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UNIMPL_FUNC(_chmod)
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UNIMPL_FUNC(_chdir)
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UNIMPL_FUNC(_getcwd)
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UNIMPL_FUNC(_sysconf)
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"j unimplemented_syscall\n"
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);
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void unimplemented_syscall()
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{
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const char *p = "Unimplemented system call called!\n";
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while (*p)
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*(volatile int*)0x10000000 = *(p++);
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asm volatile ("ebreak");
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__builtin_unreachable();
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}
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ssize_t _read(int file, void *ptr, size_t len)
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{
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// always EOF
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return 0;
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}
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ssize_t _write(int file, const void *ptr, size_t len)
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{
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const void *eptr = ptr + len;
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while (ptr != eptr)
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*(volatile int*)0x10000000 = *(char*)(ptr++);
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return len;
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}
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int _close(int file)
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{
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// close is called before _exit()
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return 0;
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}
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int _fstat(int file, struct stat *st)
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{
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// fstat is called during libc startup
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errno = ENOENT;
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return -1;
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}
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void *_sbrk(ptrdiff_t incr)
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{
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extern unsigned char _end[]; // Defined by linker
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static unsigned long heap_end;
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if (heap_end == 0)
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heap_end = (long)_end;
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heap_end += incr;
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return (void *)(heap_end - incr);
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}
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void _exit(int exit_status)
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{
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asm volatile ("ebreak");
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__builtin_unreachable();
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}
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@ -0,0 +1,140 @@
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`timescale 1 ns / 1 ps
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`undef VERBOSE_MEM
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//`undef WRITE_VCD
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`undef MEM8BIT
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// define the size of our ROM
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// simulates ROM by suppressing writes below this address
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`define ROM_SIZE 32'h0001_00FF
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module testbench;
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reg clk = 1;
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reg resetn = 0;
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wire trap;
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always #5 clk = ~clk;
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initial begin
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repeat (100) @(posedge clk);
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resetn <= 1;
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end
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wire mem_valid;
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wire mem_instr;
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reg mem_ready;
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wire [31:0] mem_addr;
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wire [31:0] mem_wdata;
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wire [3:0] mem_wstrb;
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reg [31:0] mem_rdata;
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`include "firmware_dbg.v"
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picorv32 #(
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.COMPRESSED_ISA(1),
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.PROGADDR_RESET(32'h100)
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) uut (
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.clk (clk ),
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.resetn (resetn ),
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.trap (trap ),
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.mem_valid (mem_valid ),
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.mem_instr (mem_instr ),
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.mem_ready (mem_ready ),
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.mem_addr (mem_addr ),
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.mem_wdata (mem_wdata ),
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.mem_wstrb (mem_wstrb ),
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.mem_rdata (mem_rdata )
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);
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localparam MEM_SIZE = 4*1024*1024;
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`ifdef MEM8BIT
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reg [7:0] memory [0:MEM_SIZE-1];
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initial
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$readmemh("firmware.hex", memory);
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end
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`else
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reg [31:0] memory [0:MEM_SIZE/4-1];
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integer x;
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// simulate hardware assist of clearing RAM and copying ROM data into
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// memory
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initial
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begin
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// clear memory
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for (x=0; x<MEM_SIZE/4; x=x+1) memory[x] = 0;
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// load rom contents
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$readmemh("firmware32.hex", memory);
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// copy .data section
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for (x=0; x<(`C_SYM__BSS_START - `C_SYM___GLOBAL_POINTER); x=x+4)
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memory[(`C_SYM___GLOBAL_POINTER+x)/4] = memory[(`C_SYM__DATA_LMA+x)/4];
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end
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`endif
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always @(posedge clk) begin
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mem_ready <= 0;
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if (mem_valid && !mem_ready) begin
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mem_ready <= 1;
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mem_rdata <= 'bx;
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case (1)
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mem_addr < MEM_SIZE: begin
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`ifdef MEM8BIT
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if (|mem_wstrb) begin
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if (mem_wstrb[0]) memory[mem_addr + 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr + 1] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr + 2] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr + 3] <= mem_wdata[31:24];
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end else begin
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mem_rdata <= {memory[mem_addr+3], memory[mem_addr+2], memory[mem_addr+1], memory[mem_addr]};
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end
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`else
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if ((|mem_wstrb) && (mem_addr >= `ROM_SIZE)) begin
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if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
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if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
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if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
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if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
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end else begin
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mem_rdata <= memory[mem_addr >> 2];
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end
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`endif
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end
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mem_addr == 32'h 1000_0000: begin
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$write("%c", mem_wdata[7:0]);
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end
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endcase
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end
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if (mem_valid && mem_ready) begin
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`ifdef FIRMWARE_DEBUG_ADDR
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firmware_dbg(mem_addr);
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`endif
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if ((mem_wstrb == 4'h0) && (mem_rdata === 32'bx)) $display("READ FROM UNITIALIZED ADDR=%x", mem_addr);
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`ifdef VERBOSE_MEM
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if (|mem_wstrb)
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$display("WR: ADDR=%x DATA=%x MASK=%b", mem_addr, mem_wdata, mem_wstrb);
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else
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$display("RD: ADDR=%x DATA=%x%s", mem_addr, mem_rdata, mem_instr ? " INSN" : "");
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`endif
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if (^mem_addr === 1'bx ||
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(mem_wstrb[0] && ^mem_wdata[ 7: 0] == 1'bx) ||
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(mem_wstrb[1] && ^mem_wdata[15: 8] == 1'bx) ||
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(mem_wstrb[2] && ^mem_wdata[23:16] == 1'bx) ||
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(mem_wstrb[3] && ^mem_wdata[31:24] == 1'bx)) begin
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$display("CRITICAL UNDEF MEM TRANSACTION");
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$finish;
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end
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end
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end
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`ifdef WRITE_VCD
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initial begin
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$dumpfile("testbench.vcd");
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$dumpvars(0, testbench);
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end
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`endif
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always @(posedge clk) begin
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if (resetn && trap) begin
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repeat (10) @(posedge clk);
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$display("TRAP");
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$finish;
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end
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end
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endmodule
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