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Do not peek into core for cycle count in WB testbench 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-06-03 08:17:08 +02:00
parent f3a42746ca
commit 3d36751b88
1 changed files with 5 additions and 2 deletions
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7
testbench_wb.v
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@ -70,10 +70,13 @@ module picorv32_wrapper #(
reg [31:0] irq;
wire mem_instr;
reg [15:0] count_cycle = 0;
always @(posedge wb_clk) count_cycle <= !wb_rst ? count_cycle + 1 : 0;
always @* begin
irq = 0;
irq[4] = &uut.picorv32_core.count_cycle[12:0];
irq[5] = &uut.picorv32_core.count_cycle[15:0];
irq[4] = &count_cycle[12:0];
irq[5] = &count_cycle[15:0];
end
wire [31:0] wb_m2s_adr;